linux-kernel - Re: [PATCH 02/10] arm64: dts: qcom: Add base SM8550 dtsi

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Date:   Thu, 17 Nov 2022 13:50:38 +0100
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Abel Vesa <abel.vesa@...aro.org>, Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...aro.org>,
        Rob Herring <robh@...nel.org>,
        Neil Armstrong <neil.armstrong@...aro.org>
Cc:     linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        "vkoul@...nel.org" <vkoul@...nel.org>,
        Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
Subject: Re: [PATCH 02/10] arm64: dts: qcom: Add base SM8550 dtsi

On 16/11/2022 11:31, Abel Vesa wrote:
> Add base dtsi for SM8550 SoC and includes base description of
> CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved
> memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq,
> interconnect, thermal sensor, cpu cooling maps and SMMU nodes
> which helps boot to shell with console on boards with this SoC.
> 
> Co-developed-by: Neil Armstrong <neil.armstrong@...aro.org>
> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
> Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
> ---
>  arch/arm64/boot/dts/qcom/sm8550.dtsi | 3986 ++++++++++++++++++++++++++
>  1 file changed, 3986 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/sm8550.dtsi
> 

Thank you for your patch. There is something to discuss/improve.

> +
> +		pmu@...b6400 {
> +			compatible = "qcom,sm8550-cpu-bwmon", "qcom,msm8998-bwmon";
> +			reg = <0x0 0x240b6400 0x0 0x600>;
> +			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
> +			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
> +
> +			operating-points-v2 = <&cpu_bwmon_opp_table>;
> +
> +			cpu_bwmon_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-0 {
> +					opp-peak-kBps = <4577000>;
> +				};
> +				opp-1 {
> +					opp-peak-kBps = <7110000>;
> +				};
> +				opp-2 {
> +					opp-peak-kBps = <9155000>;
> +				};
> +				opp-3 {
> +					opp-peak-kBps = <12298000>;
> +				};
> +				opp-4 {
> +					opp-peak-kBps = <14236000>;
> +				};
> +				opp-5 {
> +					opp-peak-kBps = <16265000>;
> +				};
> +			};
> +		};
> +
> +		pmu@...91000 {

Nodes should be ordered by the address. Mostly they are, but at least
BWMONs are not.

> +			compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
> +			reg = <0x0 0x24091000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> +			interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
> +
> +			operating-points-v2 = <&llcc_bwmon_opp_table>;
> +
> +			llcc_bwmon_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-0 {
> +					opp-peak-kBps = <2086000>;
> +

Drop empty lines here and in places below.

> +				};
> +				opp-1 {
> +					opp-peak-kBps = <2929000>;
> +
> +				};
> +				opp-2 {
> +					opp-peak-kBps = <5931000>;
> +
> +				};
> +				opp-3 {
> +					opp-peak-kBps = <6515000>;
> +
> +				};
> +				opp-4 {
> +					opp-peak-kBps = <7980000>;
> +
> +				};
> +				opp-5 {
> +					opp-peak-kBps = <10437000>;
> +
> +				};
> +				opp-6 {
> +					opp-peak-kBps = <12157000>;
> +
> +				};
> +				opp-7 {
> +					opp-peak-kBps = <14060000>;
> +
> +				};
> +				opp-8 {
> +					opp-peak-kBps = <16113000>;
> +
> +				};
> +			};


Best regards,
Krzysztof