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Message-ID: <22398efc-15c2-4cc5-87a1-7c47c762b283@intel.com>
Date: Fri, 18 Nov 2022 10:11:35 -0800
From: Dave Hansen <dave.hansen@...el.com>
To: Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>,
Andrew Cooper <Andrew.Cooper3@...rix.com>,
thomas.lendacky@....com, "H. Peter Anvin" <hpa@...or.com>,
hdegoede@...hat.com, Ingo Molnar <mingo@...hat.com>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>, x86@...nel.org,
Pavel Machek <pavel@....cz>,
Dave Hansen <dave.hansen@...ux.intel.com>,
David.Kaplan@....com, Borislav Petkov <bp@...en8.de>
Cc: linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
Daniel Sneddon <daniel.sneddon@...ux.intel.com>,
antonio.gomez.iglesias@...ux.intel.com
Subject: Re: [PATCH v3 1/2] x86/tsx: Add feature bit for TSX control MSR
support
On 11/15/22 11:17, Pawan Gupta wrote:
> Support for TSX control MSR is enumerated in MSR_IA32_ARCH_CAPABILITIES.
> This is different from how other CPU features are enumerated i.e. via
> CPUID. Currently a call to tsx_ctrl_is_supported() is required for
> enumerating the feature. In the absence of feature bit for TSX control,
> any code that relies on checking feature bits directly will not work.
>
> In preparation for adding a feature bit check in MSR save/restore during
> suspend/resume, set a new feature bit X86_FEATURE_TSX_CTRL when
> MSR_IA32_TSX_CTRL is present. Also make tsx_ctrl_is_supported() use the
> new feature bit to avoid any overhead of reading the MSR.
Reviewed-by: Dave Hansen <dave.hansen@...ux.intel.com>
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