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Message-ID: <20221118182752.7ovqckwwle3azzrc@desk>
Date:   Fri, 18 Nov 2022 10:27:52 -0800
From:   Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
To:     Dave Hansen <dave.hansen@...el.com>
Cc:     Andrew Cooper <Andrew.Cooper3@...rix.com>, thomas.lendacky@....com,
        "H. Peter Anvin" <hpa@...or.com>, hdegoede@...hat.com,
        Ingo Molnar <mingo@...hat.com>,
        "Rafael J. Wysocki" <rafael@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>, x86@...nel.org,
        Pavel Machek <pavel@....cz>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        David.Kaplan@....com, Borislav Petkov <bp@...en8.de>,
        linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
        Daniel Sneddon <daniel.sneddon@...ux.intel.com>,
        antonio.gomez.iglesias@...ux.intel.com
Subject: Re: [PATCH v3 2/2] x86/pm: Add enumeration check before spec MSRs
 save/restore setup

On Fri, Nov 18, 2022 at 10:12:32AM -0800, Dave Hansen wrote:
>On 11/15/22 11:17, Pawan Gupta wrote:
>> To fix this, add the corresponding X86_FEATURE bit for each MSR.  Avoid
>> trying to manipulate the MSR when the feature bit is clear. This
>> required adding a X86_FEATURE bit for MSRs that do not have one already,
>> but it's a small price to pay.
>>
>> Fixes: 73924ec4d560 ("x86/pm: Save the MSR validity status at context setup")
>> Reported-by: Hans de Goede <hdegoede@...hat.com>
>> Signed-off-by: Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
>> Cc: stable@...nel.org
>
>Thanks for fixing this up.  The X86_FEATURE approach is a good one.  The
>"poking at random MSRs" always seemed a bit wonky.
>
>Reviewed-by: Dave Hansen <dave.hansen@...ux.intel.com>

Thanks.

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