linux-kernel - Re: [PATCH RESEND 2/2] thermal: intel: Protect clearing of thermal status bits

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Message-ID: <CAJZ5v0j=LUkTtcQb3YVN0R3W4p7Cg-+wU8EAW75wz7bSTXhp4Q@mail.gmail.com>
Date:   Fri, 18 Nov 2022 20:49:34 +0100
From:   "Rafael J. Wysocki" <rafael@...nel.org>
To:     srinivas pandruvada <srinivas.pandruvada@...ux.intel.com>
Cc:     "Rafael J. Wysocki" <rafael@...nel.org>, daniel.lezcano@...aro.org,
        amitk@...nel.org, rui.zhang@...el.com, linux-pm@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
Subject: Re: [PATCH RESEND 2/2] thermal: intel: Protect clearing of thermal
 status bits

On Fri, Nov 18, 2022 at 8:40 PM srinivas pandruvada
<srinivas.pandruvada@...ux.intel.com> wrote:
>
> On Fri, 2022-11-18 at 18:57 +0100, Rafael J. Wysocki wrote:
> > On Wed, Nov 16, 2022 at 3:54 AM Srinivas Pandruvada
> > <srinivas.pandruvada@...ux.intel.com> wrote:
> > >
> > > The clearing of the package thermal status is done by Read-Modify-
> > > Write
> > > operation. This may result in clearing of some new status bits
> > > which are
> > > being or about to be processed.
> > >
> > > For example, while clearing of HFI status, after read of thermal
> > > status
> > > register, a new thermal status bit is set by the hardware. But
> > > during
> > > write back, the newly generated status bit will be set to 0 or
> > > cleared.
> > > So, it is not safe to do read-modify-write.
> > >
> > > Since thermal status Read-Write bits can be set to only 0 not 1, it
> > > is
> > > safe to set all other bits to 1 which are not getting cleared.
> > >
> > > Create a common interface for clearing package thermal status bits.
> > > Use
> > > this interface to replace existing code to clear thermal package
> > > status
> > > bits.
> > >
> > > It is safe to call from different CPUs without protection as there
> > > is no
> > > read-modify-write. Also wrmsrl results in just single instruction.
> > > For
> > > example while CPU 0 and CPU 3 are clearing bit 1 and 3
> > > respectively. If
> > > CPU 3 wins the race, it will write 0x4000aa2, then CPU 1 will write
> > > 0x4000aa8. The bits which are not part of clear are set to 1. The
> > > default
> > > mask for bits, which can be written here is 0x4000aaa.
> > >
> > > Signed-off-by: Srinivas Pandruvada
> > > <srinivas.pandruvada@...ux.intel.com>
> > > Reviewed-by: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
> >
> > How urgent is this?  Would 6.2 be sufficient?
> >
> Not urgent. 6.2 should be enough.

OK

> > Also, do you want it to go into -stable?
> Yes.

Which series?