linux-kernel - RE: [PATCH v4 4/9] cpufreq: amd_pstate: implement Pstate EPP support for the AMD processors

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Message-ID: <DM4PR12MB5278668BD034D950AB7416AB9C099@DM4PR12MB5278.namprd12.prod.outlook.com>
Date:   Fri, 18 Nov 2022 03:54:29 +0000
From:   "Yuan, Perry" <Perry.Yuan@....com>
To:     "Karny, Wyes" <Wyes.Karny@....com>,
        "rafael.j.wysocki@...el.com" <rafael.j.wysocki@...el.com>,
        "Limonciello, Mario" <Mario.Limonciello@....com>,
        "Huang, Ray" <Ray.Huang@....com>,
        "viresh.kumar@...aro.org" <viresh.kumar@...aro.org>
CC:     "Sharma, Deepak" <Deepak.Sharma@....com>,
        "Fontenot, Nathan" <Nathan.Fontenot@....com>,
        "Deucher, Alexander" <Alexander.Deucher@....com>,
        "Huang, Shimmer" <Shimmer.Huang@....com>,
        "Du, Xiaojian" <Xiaojian.Du@....com>,
        "Meng, Li (Jassmine)" <Li.Meng@....com>,
        "linux-pm@...r.kernel.org" <linux-pm@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v4 4/9] cpufreq: amd_pstate: implement Pstate EPP support
 for the AMD processors

[AMD Official Use Only - General]



> -----Original Message-----
> From: Karny, Wyes <Wyes.Karny@....com>
> Sent: Thursday, November 17, 2022 10:03 PM
> To: Yuan, Perry <Perry.Yuan@....com>; rafael.j.wysocki@...el.com;
> Limonciello, Mario <Mario.Limonciello@....com>; Huang, Ray
> <Ray.Huang@....com>; viresh.kumar@...aro.org
> Cc: Sharma, Deepak <Deepak.Sharma@....com>; Fontenot, Nathan
> <Nathan.Fontenot@....com>; Deucher, Alexander
> <Alexander.Deucher@....com>; Huang, Shimmer
> <Shimmer.Huang@....com>; Du, Xiaojian <Xiaojian.Du@....com>; Meng, Li
> (Jassmine) <Li.Meng@....com>; linux-pm@...r.kernel.org; linux-
> kernel@...r.kernel.org
> Subject: Re: [PATCH v4 4/9] cpufreq: amd_pstate: implement Pstate EPP support
> for the AMD processors
> 
> Hi Perry,
> 
> On 11/10/2022 11:28 PM, Perry Yuan wrote:
> [snip]
> > +
> > +static ssize_t store_energy_performance_preference(
> > +		struct cpufreq_policy *policy, const char *buf, size_t count) {
> > +	struct amd_cpudata *cpudata = policy->driver_data;
> > +	char str_preference[21];
> > +	ssize_t ret;
> > +	u32 epp = 0;
> 
> Here `epp` is a unused variable.
>  [snip]
> > @@ -657,6 +1281,20 @@ static int __init amd_pstate_param(char *str)
> >  	if (!str)
> >  		return -EINVAL;
> >
> > +	/*
> > +	 * Disable amd-pstate driver by default for now
> > +	 * append amd-pstate=active or amd-pstate=active
> > +	 * to enable driver loaded
> > +	 */
> > +	if (!strcmp(str, "active")) {
> > +		cppc_load = 1;
> > +		default_pstate_driver = &amd_pstate_epp_driver;
> > +	} else if (!strcmp(str, "passive")) {
> > +		epp_off = 1;
> > +		cppc_load = 1;
> > +		default_pstate_driver = &amd_pstate_driver;
> > +	}
> > +
> >  	/*
> >  	 * support shared memory type CPPC which has no MSR function.
> >  	 * enable amd-pstate on processors with shared memory solution
> 
> In the shared memory support section also `cppc_load` has to be set otherwise
> amd_pstate=legacy_cppc will not work.
If the patches just got reviewed are accepted, the legacy_cppcc will not be needed any more.
I  will rebase the EPP patches based on the that. 


> 
> if (!strcmp(str, "legacy_cppc")) {
> 	shared_mem = true;
> 	cppc_load = 1;
> }

Previous plan was to add two parameters to kernel command line, 
passive or active  and legacy_cppc for shared memory platform.

> 
> 
> --
> Thanks & Regards,
> Wyes