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Message-ID: <Y3oExmuiH95NWGUL@spud>
Date: Sun, 20 Nov 2022 10:43:18 +0000
From: Conor Dooley <conor@...nel.org>
To: Jisheng Zhang <jszhang@...nel.org>
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Jiri Slaby <jirislaby@...nel.org>,
linux-serial@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org
Subject: Re: [PATCH 4/7] riscv: add the Bouffalolab SoC family Kconfig option
On Sun, Nov 20, 2022 at 04:21:11PM +0800, Jisheng Zhang wrote:
> The Bouffalolab bl808 SoC contains three riscv CPUs, namely M0, D0 and
> LP. The D0 is 64bit RISC-V GC compatible, so can run linux.
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
Could you also add this new SOC_BOUFFALOLAB symbol to defconfig please?
>
> Signed-off-by: Jisheng Zhang <jszhang@...nel.org>
> ---
> arch/riscv/Kconfig.socs | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 69774bb362d6..90256f44ed4a 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -1,5 +1,11 @@
> menu "SoC selection"
>
> +config SOC_BOUFFALOLAB
> + bool "Bouffalolab SoCs"
> + select SIFIVE_PLIC
> + help
> + This enables support for Bouffalolab SoC platforms.
> +
> config SOC_MICROCHIP_POLARFIRE
> bool "Microchip PolarFire SoCs"
> select MCHP_CLK_MPFS
> --
> 2.37.2
>
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