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Message-Id: <20221121105210.68596-2-shradha.t@samsung.com>
Date: Mon, 21 Nov 2022 16:22:05 +0530
From: Shradha Todi <shradha.t@...sung.com>
To: bhelgaas@...gle.com, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, kishon@...com, vkoul@...nel.org,
lpieralisi@...nel.org, kw@...ux.com, mani@...nel.org,
arnd@...db.de, gregkh@...uxfoundation.org, alim.akhtar@...sung.com,
ajaykumar.rs@...sung.com, rcsekar@...sung.com,
sriranjani.p@...sung.com, bharat.uppal@...sung.com,
s.prashar@...sung.com, aswani.reddy@...sung.com,
pankaj.dubey@...sung.com, p.rajanbabu@...sung.com,
niyas.ahmed@...sung.com, chanho61.park@...sung.com
Cc: linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org,
Shradha Todi <shradha.t@...sung.com>
Subject: [PATCH 1/6] dt-bindings: phy: Add PCIe PHY bindings for FSD
Document the PCIe PHY device tree bindings for Tesla
FSD SoC
Signed-off-by: Shradha Todi <shradha.t@...sung.com>
---
.../bindings/phy/phy-tesla-pcie.yaml | 75 +++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-tesla-pcie.yaml
diff --git a/Documentation/devicetree/bindings/phy/phy-tesla-pcie.yaml b/Documentation/devicetree/bindings/phy/phy-tesla-pcie.yaml
new file mode 100644
index 000000000000..8fa9a050af7a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-tesla-pcie.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/phy-tesla-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tesla FSD SoC PCIe PHY
+
+maintainers:
+ - Shradha Todi <shradha.t@...sung.com>
+
+properties:
+ "#phy-cells":
+ const: 0
+
+ compatible:
+ enum:
+ - tesla,fsd-pcie-phy
+
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ reg-names:
+ minItems: 2
+ maxItems: 2
+ items:
+ enum: [phy, pcs]
+ description: |
+ phy is the register access to PMA layer
+ pcs is the register access to PCS layer
+
+ phy-mode:
+ description: |
+ Defines the bifurcation mode of the PHY
+
+ tesla,pmureg-phandle:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: phandle for PMU system controller interface used to
+ control PMU register bits for PCIe PHY
+
+ tesla,pcie-sysreg:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: phandle for system control registers, used to
+ control phy signals at system level
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - reg-names
+ - phy-mode
+ - tesla,pmureg-phandle
+ - tesla,pcie-sysreg
+
+additionalProperties: false
+
+examples:
+ - |
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie_phy0: pcie-phy@...80000 {
+ compatible = "tesla,fsd-pcie-phy";
+ #phy-cells = <0>;
+ reg = <0x0 0x15080000 0x0 0x2000>, <0x0 0x150A0000 0x0 0x1000>;
+ reg-names = "phy", "pcs";
+ tesla,pmureg-phandle = <&pmu_system_controller>;
+ tesla,pcie-sysreg = <&sysreg_fsys0>;
+ phy-mode = <0>;
+ status = "disabled";
+ };
+ };
+...
--
2.17.1
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