lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <Y3uGJ3D4OH0vPLqj@errol.ini.cmu.edu>
Date:   Mon, 21 Nov 2022 09:07:35 -0500
From:   "Gabriel L. Somlo" <gsomlo@...il.com>
To:     Jiri Slaby <jirislaby@...nel.org>
Cc:     linux-kernel@...r.kernel.org, linux-serial@...r.kernel.org,
        gregkh@...uxfoundation.org, kgugala@...micro.com,
        mholenko@...micro.com, joel@....id.au,
        david.abdurachmanov@...il.com, florent@...oy-digital.fr,
        geert@...ux-m68k.org, ilpo.jarvinen@...ux.intel.com
Subject: Re: [PATCH v5 13/14] serial: liteuart: add IRQ support for the TX
 path

On Mon, Nov 21, 2022 at 09:58:41AM +0100, Jiri Slaby wrote:
> On 18. 11. 22, 15:55, Gabriel Somlo wrote:
> > Switch the TX path to IRQ-driven operation, while maintaining support
> > for polling mode via the poll timer.
> > 
> > Signed-off-by: Gabriel Somlo <gsomlo@...il.com>
> > Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
> ...
> > @@ -154,6 +148,8 @@ static irqreturn_t liteuart_interrupt(int irq, void *data)
> >   	isr = litex_read8(port->membase + OFF_EV_PENDING) & uart->irq_reg;
> >   	if (isr & EV_RX)
> >   		liteuart_rx_chars(port);
> > +	if (isr & EV_TX)
> > +		liteuart_tx_chars(port);
> 
> Wait, how do you ensure the OFF_EV_PENDING reg contains EV_RX and/or EV_TX
> in the polling mode?

The hardware (well, *gateware*) is coded to populate the EV_PENDING
register regardless of whether IRQs are enabled via the EV_ENABLE
register (or indeed, whether IRQs are even "wired into" the design at
all). See

https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/uart.py
and
https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/csr_eventmanager.py

for a starting point on why it's OK to just assume that...

Thanks,
--Gabriel

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ