[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <Y3yS6fCIl+0nsbOj@smile.fi.intel.com>
Date: Tue, 22 Nov 2022 11:14:17 +0200
From: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To: Rahul Tanwar <rtanwar@...linear.com>
Cc: bigeasy@...utronix.de, robh@...nel.org, tglx@...utronix.de,
mingo@...hat.com, bp@...en8.de, x86@...nel.org, hpa@...or.com,
dave.hansen@...ux.intel.com, linux-kernel@...r.kernel.org,
linux-lgm-soc@...linear.com
Subject: Re: [PATCH v3 4/4] x86/of: Add support for boot time interrupt
delivery mode configuration
On Tue, Nov 22, 2022 at 03:39:10PM +0800, Rahul Tanwar wrote:
> Presently, init/boot time interrupt delivery mode is enumerated
> only for ACPI enabled systems by parsing MADT table or for older
> systems by parsing MP table. But for OF based x86 systems, it is
> assumed & hardcoded to legacy PIC mode. This is a bug for
> platforms which are OF based but do not use 8259 compliant legacy
> PIC interrupt controller. Such platforms can not even boot because
> of this bug/hardcoding.
>
> Fix this bug by adding support for configuration of init time
> interrupt delivery mode for x86 OF based systems by introducing a
> new optional boolean property 'intel,virtual-wire-mode' for
> interrupt-controller node of local APIC. This property emulates
> IMCRP Bit 7 of MP feature info byte 2 of MP floating pointer
> structure.
>
> Defaults to legacy PIC mode if absent. Configures it to virtual
> wire compatibility mode if present.
> Fixes: 3879a6f32948 ("x86: dtb: Add early parsing of IO_APIC")
If it was never working, there is nothing to fix.
OTOH, without Cc: stable@ this is up to stable maintainers to
backport.
> Suggested-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
I definitely haven't suggested this fix.
...
The code looks good to me.
--
With Best Regards,
Andy Shevchenko
Powered by blists - more mailing lists