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Message-ID: <Y3zH/etMuIQ5l+SK@smile.fi.intel.com>
Date:   Tue, 22 Nov 2022 15:00:45 +0200
From:   Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To:     Mika Westerberg <mika.westerberg@...ux.intel.com>,
        Uwe Kleine-König 
        <u.kleine-koenig@...gutronix.de>,
        Hans de Goede <hdegoede@...hat.com>,
        Thierry Reding <thierry.reding@...il.com>,
        linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org,
        linux-pwm@...r.kernel.org
Cc:     Linus Walleij <linus.walleij@...aro.org>
Subject: Re: [PATCH v5 0/7] pinctrl: intel: Enable PWM optional feature

On Thu, Nov 17, 2022 at 01:07:59PM +0200, Andy Shevchenko wrote:
> 
> This is a continuation of the previously applied PWM LPSS cleanup series.
> Now, we would like to enable PWM optional feature that may be embedded
> into Intel pin control IPs (starting from Sky Lake platforms).
> 
> I would like to route this via Intel pin control tree with issuing
> an immutable branch for both PINCTRL and PWM subsystems, but I'm
> open for other suggestions.
> 
> Hans, I dared to leave your Rb tags, however the patches are slightly
> differ, because of the Uwe's suggestion on how to handle the missing
> headers. I hope you are okay with that. If not, please comment what
> must be amended then.
> 
> Uwe, the patches 3 and 6 still need your blessing.

Uwe, do you think they are ready to go?

-- 
With Best Regards,
Andy Shevchenko


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