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Message-ID: <a27a99fe-e85b-424d-bf75-835abf1f20d1@ti.com>
Date: Tue, 22 Nov 2022 19:33:25 +0530
From: Vaishnav Achath <vaishnav.a@...com>
To: Matt Ranostay <mranostay@...com>, <nm@...com>, <afd@...com>,
<vigneshr@...com>, <kristo@...nel.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <s-vadapalli@...com>,
<r-gunasekaran@...com>
CC: <linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
Vaishnav Achath <vaishnav.a@...com>
Subject: Re: [PATCH v7 3/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support
of OSPI
On 22/11/22 15:46, Matt Ranostay wrote:
> From: Aswath Govindraju <a-govindraju@...com>
>
> Add support for two instance of OSPI in J721S2 SoC.
>
> Signed-off-by: Aswath Govindraju <a-govindraju@...com>
> Signed-off-by: Matt Ranostay <mranostay@...com>
> ---
> .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> index 0af242aa9816..a588ab8d867b 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> @@ -306,4 +306,44 @@ cpts@...00 {
> ti,cpts-periodic-outputs = <2>;
> };
> };
> +
> + fss: syscon@...00000 {
> + compatible = "simple-bus";
> + reg = <0x00 0x47000000 0x00 0x100>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + ospi0: spi@...40000 {
> + compatible = "ti,am654-ospi", "cdns,qspi-nor";
> + reg = <0x00 0x47040000 0x00 0x100>,
> + <0x5 0x0000000 0x1 0x0000000>;
> + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
> + cdns,fifo-depth = <256>;
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0x0>;
> + clocks = <&k3_clks 109 5>;
> + assigned-clocks = <&k3_clks 109 5>;
> + assigned-clock-parents = <&k3_clks 109 7>;
> + assigned-clock-rates = <166666666>;
> + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + ospi1: spi@...50000 {
> + compatible = "ti,am654-ospi", "cdns,qspi-nor";
> + reg = <0x00 0x47050000 0x00 0x100>,
> + <0x7 0x0000000 0x1 0x0000000>;
> + interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
> + cdns,fifo-depth = <256>;
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0x0>;
> + clocks = <&k3_clks 110 5>;
> + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
Reviewed-by: Vaishnav Achath <vaishnav.a@...com>
> +
> + };
> };
--
Regards,
Vaishnav
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