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Message-ID: <20221123135531.23221-6-allen-kh.cheng@mediatek.com>
Date: Wed, 23 Nov 2022 21:55:31 +0800
From: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
To: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Rob Herring <robh+dt@...nel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski@...aro.org>
CC: <Project_Global_Chrome_Upstream_Group@...iatek.com>,
<linux-usb@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>, <hsinyi@...omium.org>,
Allen-KH Cheng <allen-kh.cheng@...iatek.com>
Subject: [PATCH v2 5/5] arm64: dts: mt8186: Add mtu3 nodes
Add mtu3 nodes for mt8186 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 75 ++++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 4a2f7ad3c6f0..1761211f1464 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -848,6 +848,43 @@
status = "disabled";
};
+ ssusb0: usb@...01000 {
+ compatible = "mediatek,mt8186-mtu3",
+ "mediatek,mtu3";
+ reg = <0 0x11201000 0 0x2dff>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ clocks = <&topckgen CLK_TOP_USB_TOP>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>,
+ <&infracfg_ao CLK_INFRA_AO_ICUSB>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+ interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port0 PHY_TYPE_USB2>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb_host0: usb@...00000 {
+ compatible = "mediatek,mt8186-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>;
+ reg-names = "mac";
+ clocks = <&topckgen CLK_TOP_USB_TOP>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>,
+ <&infracfg_ao CLK_INFRA_AO_ICUSB>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+ interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,syscon-wakeup = <&pericfg 0x420 2>;
+ wakeup-source;
+ status = "disabled";
+ };
+ };
+
mmc0: mmc@...30000 {
compatible = "mediatek,mt8186-mmc",
"mediatek,mt8183-mmc";
@@ -878,6 +915,44 @@
status = "disabled";
};
+ ssusb1: usb@...81000 {
+ compatible = "mediatek,mt8186-mtu3",
+ "mediatek,mtu3";
+ reg = <0 0x11281000 0 0x2dff>,
+ <0 0x11283e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>,
+ <&clk26m>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+ interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port1 PHY_TYPE_USB2>,
+ <&u3port1 PHY_TYPE_USB3>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb_host1: usb@...80000 {
+ compatible = "mediatek,mt8186-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11280000 0 0x1000>;
+ reg-names = "mac";
+ clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>,
+ <&clk26m>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck";
+ interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,syscon-wakeup = <&pericfg 0x424 2>;
+ wakeup-source;
+ status = "disabled";
+ };
+ };
+
u3phy0: t-phy@...80000 {
compatible = "mediatek,mt8186-tphy",
"mediatek,generic-tphy-v2";
--
2.18.0
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