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Message-ID: <IA1PR11MB60979EB9FBE4C95381BF9F8A9B0C9@IA1PR11MB6097.namprd11.prod.outlook.com>
Date: Wed, 23 Nov 2022 18:17:23 +0000
From: "Yu, Fenghua" <fenghua.yu@...el.com>
To: Babu Moger <babu.moger@....com>, "corbet@....net" <corbet@....net>,
"Chatre, Reinette" <reinette.chatre@...el.com>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"mingo@...hat.com" <mingo@...hat.com>,
"bp@...en8.de" <bp@...en8.de>
CC: "dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
"x86@...nel.org" <x86@...nel.org>, "hpa@...or.com" <hpa@...or.com>,
"paulmck@...nel.org" <paulmck@...nel.org>,
"akpm@...ux-foundation.org" <akpm@...ux-foundation.org>,
"quic_neeraju@...cinc.com" <quic_neeraju@...cinc.com>,
"rdunlap@...radead.org" <rdunlap@...radead.org>,
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"Bae, Chang Seok" <chang.seok.bae@...el.com>,
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<pawan.kumar.gupta@...ux.intel.com>,
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"Eranian, Stephane" <eranian@...gle.com>
Subject: RE: [PATCH v8 03/13] x86/cpufeatures: Add Bandwidth Monitoring Event
Configuration feature flag
Hi, Babu,
> Newer AMD processors support the new feature Bandwidth Monitoring Event
> Configuration (BMEC).
>
> The feature support is identified via CPUID Fn8000_0020_EBX_x0 (ECX=0).
> Bits Field Name Description
> 3 EVT_CFG Bandwidth Monitoring Event Configuration (BMEC)
>
> Currently, the bandwidth monitoring events mbm_total_bytes and
> mbm_local_bytes are set to count all the total and local reads/writes
> respectively. With the introduction of slow memory, the two counters are not
> enough to count all the different types of memory events. With the feature
> BMEC, the users have the option to configure mbm_total_bytes and
> mbm_local_bytes to count the specific type of events.
>
> Each BMEC event has a configuration MSR, QOS_EVT_CFG (0xc000_0400h +
> EventID) which contains one field for each bandwidth type that can be used to
> configure the bandwidth event to track any combination of supported
> bandwidth types. The event will count requests from every bandwidth type bit
> that is set in the corresponding configuration register.
>
> Following are the types of events supported:
>
> ==== ========================================================
> Bits Description
> ==== ========================================================
> 6 Dirty Victims from the QOS domain to all types of memory
> 5 Reads to slow memory in the non-local NUMA domain
> 4 Reads to slow memory in the local NUMA domain
> 3 Non-temporal writes to non-local NUMA domain
> 2 Non-temporal writes to local NUMA domain
> 1 Reads to memory in the non-local NUMA domain
> 0 Reads to memory in the local NUMA domain
> ==== ========================================================
>
> By default, the mbm_total_bytes configuration is set to 0x7F to count all the
> event types and the mbm_local_bytes configuration is set to
> 0x15 to count all the local memory events.
>
> Feature description is available in the specification, "AMD64 Technology
> Platform Quality of Service Extensions, Revision: 1.03 Publication
>
> Link: https://www.amd.com/en/support/tech-docs/amd64-technology-
> platform-quality-service-extensions
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
> Signed-off-by: Babu Moger <babu.moger@....com>
> ---
> arch/x86/include/asm/cpufeatures.h | 1 +
> arch/x86/kernel/cpu/cpuid-deps.c | 1 +
> arch/x86/kernel/cpu/scattered.c | 1 +
> 3 files changed, 3 insertions(+)
>
> diff --git a/arch/x86/include/asm/cpufeatures.h
> b/arch/x86/include/asm/cpufeatures.h
> index d68b4c9c181d..6732ca0117be 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -306,6 +306,7 @@
> #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM
> exit when EIBRS is enabled */
> #define X86_FEATURE_CALL_DEPTH (11*32+18) /* "" Call depth
> tracking for RSB stuffing */
> #define X86_FEATURE_SMBA (11*32+19) /* Slow Memory
> Bandwidth Allocation */
> +#define X86_FEATURE_BMEC (11*32+20) /* AMD Bandwidth
> Monitoring Event Configuration (BMEC) */
>
> /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
> #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI
> instructions */
> diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-
> deps.c
> index c881bcafba7d..4555f9596ccf 100644
> --- a/arch/x86/kernel/cpu/cpuid-deps.c
> +++ b/arch/x86/kernel/cpu/cpuid-deps.c
> @@ -68,6 +68,7 @@ static const struct cpuid_dep cpuid_deps[] = {
> { X86_FEATURE_CQM_OCCUP_LLC,
> X86_FEATURE_CQM_LLC },
> { X86_FEATURE_CQM_MBM_TOTAL,
> X86_FEATURE_CQM_LLC },
> { X86_FEATURE_CQM_MBM_LOCAL,
> X86_FEATURE_CQM_LLC },
> + { X86_FEATURE_BMEC, X86_FEATURE_CQM_LLC },
Shouldn't X86_FEATURE_BMEC really depend on X86_FEATURE_CQM_MBM_LOCAL and _TOTAL?
CQM_MBM_LOCAL and/or _TOTAL can be disabled but CQM_LLC can still be enabled. In this
case, BMEC shouldn't be enabled, right? But with this patch, BMEC will be enabled but it won't
work well as CQM_MBM_TOTAL/_LOCAL are not enabled.
You may remove the above line and add these two lines:
+ { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_TOTAL },
+ { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_LOCAL },
Thanks.
-Fenghua
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