linux-kernel - Re: [PATCH v2 02/10] arm64: dts: qcom: Add base SM8550 dtsi

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Date:   Thu, 24 Nov 2022 16:40:52 +0100
From:   Konrad Dybcio <konrad.dybcio@...aro.org>
To:     Sai Prakash Ranjan <quic_saipraka@...cinc.com>,
        Abel Vesa <abel.vesa@...aro.org>,
        Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Neil Armstrong <neil.armstrong@...aro.org>
Cc:     Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org
Subject: Re: [PATCH v2 02/10] arm64: dts: qcom: Add base SM8550 dtsi



On 24.11.2022 16:39, Sai Prakash Ranjan wrote:
> Hi,
> 
> On 11/24/2022 7:26 PM, Abel Vesa wrote:
>> Add base dtsi for SM8550 SoC and includes base description of
>> CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved
>> memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq,
>> interconnect, thermal sensor, cpu cooling maps and SMMU nodes
>> which helps boot to shell with console on boards with this SoC.
>>
>> Co-developed-by: Neil Armstrong <neil.armstrong@...aro.org>
>> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
>> Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
>> ---
> 
> <snip>...
> 
>> +    timer {
>> +        compatible = "arm,armv8-timer";
>> +        interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> +                 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> +                 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> +                 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> 
> This last interrupt must be Hypervisor physical irq(10) and 12 is Hyp virtual irq, so please change it to 10. I guess you got this from downstream but it's not right and they don't boot kernel in EL2.
Does non-CrOS 8550 FW allow Linux to boot in EL2?

Konrad
> 
> Thanks,
> Sai