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Message-ID: <20221124081221.1206167-1-mranostay@ti.com>
Date: Thu, 24 Nov 2022 00:12:16 -0800
From: Matt Ranostay <mranostay@...com>
To: <rogerq@...nel.org>, <lpieralisi@...nel.org>, <robh@...nel.org>,
<kw@...ux.com>, <bhelgaas@...gle.com>,
<krzysztof.kozlowski@...aro.org>, <vigneshr@...com>,
<tjoseph@...ence.com>, <sergio.paracuellos@...il.com>,
<pthombar@...ence.com>, <linux-pci@...r.kernel.org>
CC: <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-omap@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
Matt Ranostay <mranostay@...com>
Subject: [PATCH v7 0/5] PCI: add 4x lane support for pci-j721e controllers
Adding of additional support to Cadence PCIe controller (i.e. pci-j721e.c)
for up to 4x lanes, and reworking of driver to define maximum lanes per
board configuration.
Changes from v1:
* Reworked 'PCI: j721e: Add PCIe 4x lane selection support' to not cause
regressions on 1-2x lane platforms
Changes from v2:
* Correct dev_warn format string from %d to %u since lane count is a unsigned
integer
* Update CC list
Changes from v3:
* Use the max_lanes setting per chip for the mask size required since bootloader
could have set num_lanes to a higher value that the device tree which would leave
in an undefined state
* Reorder patches do the previous change to not break bisect
* Remove line breaking for dev_warn to allow better grepping and since no strict
80 columns anymore
Changes from v4:
* Correct invalid settings for j7200 PCIe RC + EP
* Add j784s4 configuration for selection of 4x lanes
Changes from v5:
* Dropped 'PCI: j721e: Add warnings on num-lanes misconfiguration' patch from series
* Reworded 'PCI: j721e: Add per platform maximum lane settings' commit message
* Added yaml documentation and schema checks for ti,j721e-pci-* lane checking
Changes from v6:
* Fix wordwrapping in commit messages from ~65 columns to correct 75 columns
* Re-ran get_maintainers.pl to add missing maintainers in CC
Matt Ranostay (5):
dt-bindings: PCI: ti,j721e-pci-*: add checks for num-lanes
PCI: j721e: Add per platform maximum lane settings
PCI: j721e: Add PCIe 4x lane selection support
dt-bindings: PCI: ti,j721e-pci-*: add j784s4-pci-* compatible strings
PCI: j721e: add j784s4 PCIe configuration
.../bindings/pci/ti,j721e-pci-ep.yaml | 40 +++++++++++++++--
.../bindings/pci/ti,j721e-pci-host.yaml | 40 +++++++++++++++--
drivers/pci/controller/cadence/pci-j721e.c | 44 ++++++++++++++++---
3 files changed, 113 insertions(+), 11 deletions(-)
--
2.38.GIT
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