lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Thu, 24 Nov 2022 11:40:20 +0000
From:   Mark Brown <broonie@...nel.org>
To:     Nathan Barrett-Morrison <nathan.morrison@...esys.com>
Cc:     greg.malysa@...esys.com,
        "open list:SPI SUBSYSTEM" <linux-spi@...r.kernel.org>,
        open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] spi: cadence-quadspi: Add upper limit safety check to
 baudrate divisor

On Wed, Nov 23, 2022 at 04:17:05PM -0500, Nathan Barrett-Morrison wrote:

> +	/* Maximum baud divisor */
> +	if (div > CQSPI_REG_CONFIG_BAUD_MASK)
> +		div = CQSPI_REG_CONFIG_BAUD_MASK;

This will fix the overflow of the divisor but it means that we'll be
generating a faster clock than the device asked for which might lead to
problems.  We should at the very least warn, though returning an error
would be safer.  Ideally we'd be able to adjust the input clock to the
SPI controller to allow us to divide out an appropriate clock but that's
more disruptive.

Download attachment "signature.asc" of type "application/pgp-signature" (489 bytes)

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ