linux-kernel - Re: [PATCH v2 2/2] soc: mediatek: pm-domains: Add support for mt8188

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Date:   Fri, 25 Nov 2022 03:27:19 +0000
From:   Garmin Chang (張家銘) 
        <Garmin.Chang@...iatek.com>
To:     "matthias.bgg@...il.com" <matthias.bgg@...il.com>,
        "angelogioacchino.delregno@...labora.com" 
        <angelogioacchino.delregno@...labora.com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>
CC:     "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-mediatek@...ts.infradead.org" 
        <linux-mediatek@...ts.infradead.org>,
        Project_Global_Chrome_Upstream_Group 
        <Project_Global_Chrome_Upstream_Group@...iatek.com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: Re: [PATCH v2 2/2] soc: mediatek: pm-domains: Add support for mt8188

On Tue, 2022-10-04 at 10:19 +0200, AngeloGioacchino Del Regno wrote:
> Il 28/09/22 10:43, Garmin.Chang ha scritto:
> > Add domain control data including bus protection data size
> > change due to more protection steps in mt8188.
> > 
> > Signed-off-by: Garmin.Chang <Garmin.Chang@...iatek.com>
> > ---
> >   drivers/soc/mediatek/mt8188-pm-domains.h | 623
> > +++++++++++++++++++++++
> >   drivers/soc/mediatek/mtk-pm-domains.c    |   5 +
> >   include/linux/soc/mediatek/infracfg.h    | 121 +++++
> >   3 files changed, 749 insertions(+)
> >   create mode 100644 drivers/soc/mediatek/mt8188-pm-domains.h
> > 
> > diff --git a/drivers/soc/mediatek/mt8188-pm-domains.h
> > b/drivers/soc/mediatek/mt8188-pm-domains.h
> > new file mode 100644
> > index 000000000000..63181f05457e
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mt8188-pm-domains.h
> > @@ -0,0 +1,623 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2022 MediaTek Inc.
> > + * Author: Garmin Chang <garmin.chang@...iatek.com>
> > + */
> > +
> > +#ifndef __SOC_MEDIATEK_MT8188_PM_DOMAINS_H
> > +#define __SOC_MEDIATEK_MT8188_PM_DOMAINS_H
> > +
> > +#include "mtk-pm-domains.h"
> > +#include <dt-bindings/power/mediatek,mt8188-power.h>
> > +
> > +/*
> > + * MT8188 power domain support
> > + */
> > +
> > +static const struct scpsys_domain_data scpsys_domain_data_mt8188[]
> > = {
> > +	[MT8188_POWER_DOMAIN_MFG0] = {
> > +		.name = "mfg0",
> > +		.sta_mask = BIT(1),
> > +		.ctl_offs = 0x300,
> > +		.pwr_sta_offs = 0x174,
> > +		.pwr_sta2nd_offs = 0x178,
> > +		.sram_pdn_bits = BIT(8),
> > +		.sram_pdn_ack_bits = BIT(12),
> > +		.caps = MTK_SCPD_KEEP_DEFAULT_OFF |
> > MTK_SCPD_DOMAIN_SUPPLY,
> > +	},
> > +	[MT8188_POWER_DOMAIN_MFG1] = {
> > +		.name = "mfg1",
> > +		.sta_mask = BIT(2),
> > +		.ctl_offs = 0x304,
> > +		.pwr_sta_offs = 0x174,
> > +		.pwr_sta2nd_offs = 0x178,
> > +		.sram_pdn_bits = BIT(8),
> > +		.sram_pdn_ack_bits = BIT(12),
> > +		.bp_infracfg = {
> > +			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP1,
> > +				    MT8188_TOP_AXI_PROT_EN_SET,
> > +				    MT8188_TOP_AXI_PROT_EN_CLR,
> > +				    MT8188_TOP_AXI_PROT_EN_STA),
> > +			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2
> > ,
> > +				    MT8188_TOP_AXI_PROT_EN_2_SET,
> > +				    MT8188_TOP_AXI_PROT_EN_2_CLR,
> > +				    MT8188_TOP_AXI_PROT_EN_2_STA),
> > +			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3
> > ,
> > +				    MT8188_TOP_AXI_PROT_EN_1_SET,
> > +				    MT8188_TOP_AXI_PROT_EN_1_CLR,
> > +				    MT8188_TOP_AXI_PROT_EN_1_STA),
> > +			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4
> > ,
> > +				    MT8188_TOP_AXI_PROT_EN_2_SET,
> > +				    MT8188_TOP_AXI_PROT_EN_2_CLR,
> > +				    MT8188_TOP_AXI_PROT_EN_2_STA),
> > +			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP5,
> > +				    MT8188_TOP_AXI_PROT_EN_SET,
> > +				    MT8188_TOP_AXI_PROT_EN_CLR,
> > +				    MT8188_TOP_AXI_PROT_EN_STA),
> > +			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VD
> > NR_MFG1_STEP6,
> > +				    MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VD
> > NR_SET,
> > +				    MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VD
> > NR_CLR,
> > +				    MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VD
> > NR_STA),
> > +		},
> > +		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> 
> Please add MTK_SCPD_DOMAIN_SUPPLY cap to MFG1 as well.
> For more information, please look at:
> 13bde169c6fe ("soc: mediatek: mtk-pm-domains: Allow probing vreg
> supply on two MFGs")
> 
> Regards,
> Angelo
> 

Thank you for your suggestion.

Accroding to /sys/kernel/debug/pm_genpd/pm_genpd_summary, mfg0 is the
parent of mfg1 and mfg1 is the parent of mfg2, mfg3 and mfg4.
Before the devices power on mfg2, mfg3 and mfg4, system will power on
mfg1 first. Also before the devices power on mfg1, system will power on
mfg0 first.
Because mfg0 is the root of mfg1, mfg2, mfg3 and mfg4 and
MTK_SCPD_DOMAIN_SUPPLY is configured on mfg0, so MTK_SCPD_DOMAIN_SUPPLY
is also applied on mfg1, mfg2, mfg3 and mfg4.

Thanks,
Best Regards,
Garmin