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Message-ID: <Y4Dx13KQHqyBLak3@sirena.org.uk>
Date: Fri, 25 Nov 2022 16:48:23 +0000
From: Mark Brown <broonie@...nel.org>
To: Jonathan Neuschäfer <j.neuschaefer@....net>
Cc: linux-spi@...r.kernel.org, openbmc@...ts.ozlabs.org,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 2/3] spi: wpcm-fiu: Add driver for Nuvoton WPCM450
Flash Interface Unit (FIU)
On Fri, Nov 25, 2022 at 05:33:31PM +0100, Jonathan Neuschäfer wrote:
> As to connecting non-memory chips: There is also a second, completely
> different SPI controller in this SoC, which is used on some boards (in
> factory configuration) to drive a little status LCD. I think it would be
> easiest to use that one for custom hardware extensions.
That's never stopped hardware engineers. Perhaps it's simpler for
pinmuxing, layout or other reasons in a given design.
> > If the driver were implementing regular SPI operations and advertising
> > a maximum transfer length this should just work without having to jump
> > through hoops. The core can split transfers up into sections that fit
> > within the controller limits transparently.
> As far as I'm aware, the controller is not capable of performing a pure
> read transfer, because the command byte (a byte that is written, in
> half-duplex) is always included at the start. I think this limitation
> would break your idea.
> IOW, the hoops aren't nice, but I think they're necessary.
Ah, I see. That is very limiting. I'm very surprised that the
6 byte thing works at all TBH.
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