lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Message-ID: <87zgceszp8.wl-maz@kernel.org> Date: Sat, 26 Nov 2022 11:49:23 +0000 From: Marc Zyngier <maz@...nel.org> To: Conor Dooley <conor@...nel.org> Cc: Palmer Dabbelt <palmer@...belt.com>, Anup Patel <anup@...infault.org>, Thomas Gleixner <tglx@...utronix.de>, Paul Walmsley <paul.walmsley@...ive.com>, Albert Ou <aou@...s.berkeley.edu>, linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org, Conor Dooley <conor.dooley@...rochip.com> Subject: Re: [PATCH v2 0/3] RISC-V interrupt controller select cleanup On Fri, 18 Nov 2022 10:42:58 +0000, Conor Dooley <conor@...nel.org> wrote: > > From: Conor Dooley <conor.dooley@...rochip.com> > > Hey Marc, Anup, Palmer, > > Submitted a patch yesterday defaulting the SiFive PLIC driver to > enabled [0], and in the ensuing conversation Marc suggested just doing a > select at the arch level and dropping the user selectability completely. > > Since we're already selecting SIFIVE_PLIC in Kconfig.socs for all of the > supported SoCs & selecting RISCV_INTC in the arch Kconfig itself, > patches 1 & 2 can go via the irqchip tree without any impact. > > @Anup, by the same logic - I think we can also enable the AIA stuff via > selects at the arch level? Dumping as much from Kconfig.socs as possible > is the plan, so adding them there for SOC_VIRT kinda goes contrary to > that. > > I spoke with Palmer today about putting my various bits of Kconfig.socs > cleanup on a branch, so I'll take patch 3. It's only in this series as > it is related work, rather due to any sort of dependency between the > patches. > > Thanks, > Conor. > > [0] https://lore.kernel.org/linux-riscv/86wn7tnx9a.wl-maz@kernel.org/ > > Conor Dooley (3): > irqchip/sifive-plic: remove user selectability of SIFIVE_PLIC > irqchip/riscv-intc: remove user selectability of RISCV_INTC > RISC-V: stop selecting SIFIVE_PLIC at the SoC level > > arch/riscv/Kconfig | 1 + > arch/riscv/Kconfig.socs | 5 ----- > drivers/irqchip/Kconfig | 21 ++------------------- > 3 files changed, 3 insertions(+), 24 deletions(-) For the series: Acked-by: Marc Zyngier <maz@...nel.org> Please take the whole thing via the RISC-V tree. Thanks, M. -- Without deviation from the norm, progress is not possible.
Powered by blists - more mailing lists