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Message-Id: <20221127132448.4034-4-jszhang@kernel.org>
Date: Sun, 27 Nov 2022 21:24:42 +0800
From: Jisheng Zhang <jszhang@...nel.org>
To: Rob Herring <robh+dt@...nel.org>, Conor Dooley <conor@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jiri Slaby <jirislaby@...nel.org>,
Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
Cc: linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-serial@...r.kernel.org,
Conor Dooley <conor.dooley@...rochip.com>
Subject: [PATCH v2 3/9] riscv: add the Bouffalolab SoC family Kconfig option
The Bouffalolab bl808 SoC contains three riscv CPUs, namely M0, D0 and
LP. The D0 is 64bit RISC-V GC compatible, so can run linux.
Signed-off-by: Jisheng Zhang <jszhang@...nel.org>
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
---
arch/riscv/Kconfig.socs | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 69774bb362d6..90256f44ed4a 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -1,5 +1,11 @@
menu "SoC selection"
+config SOC_BOUFFALOLAB
+ bool "Bouffalolab SoCs"
+ select SIFIVE_PLIC
+ help
+ This enables support for Bouffalolab SoC platforms.
+
config SOC_MICROCHIP_POLARFIRE
bool "Microchip PolarFire SoCs"
select MCHP_CLK_MPFS
--
2.38.1
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