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Date: Sun, 27 Nov 2022 21:24:47 +0800 From: Jisheng Zhang <jszhang@...nel.org> To: Rob Herring <robh+dt@...nel.org>, Conor Dooley <conor@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Jiri Slaby <jirislaby@...nel.org>, Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com> Cc: linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-serial@...r.kernel.org Subject: [PATCH v2 8/9] MAINTAINERS: riscv: add entry for Bouffalolab SoC Add Jisheng Zhang as Bouffalolab SoC maintainer. Signed-off-by: Jisheng Zhang <jszhang@...nel.org> --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 00ff4a2949b8..a6b04249853c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17729,6 +17729,15 @@ F: arch/riscv/ N: riscv K: riscv +RISC-V BOUFFALOLAB SOC SUPPORT +M: Jisheng Zhang <jszhang@...nel.org> +L: linux-riscv@...ts.infradead.org +S: Maintained +F: Documentation/devicetree/bindings/riscv/bouffalolab.yaml +F: Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml +F: arch/riscv/boot/dts/bouffalolab/ +F: drivers/tty/serial/bflb_uart.c + RISC-V MICROCHIP FPGA SUPPORT M: Conor Dooley <conor.dooley@...rochip.com> M: Daire McNamara <daire.mcnamara@...rochip.com> -- 2.38.1
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