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Message-ID: <Y4Of7s6UGpD0/Iga@spud>
Date: Sun, 27 Nov 2022 17:35:42 +0000
From: Conor Dooley <conor@...nel.org>
To: Jisheng Zhang <jszhang@...nel.org>
Cc: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jiri Slaby <jirislaby@...nel.org>,
Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>,
linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-serial@...r.kernel.org
Subject: Re: [PATCH v2 8/9] MAINTAINERS: riscv: add entry for Bouffalolab SoC
Hey Jisheng,
On Sun, Nov 27, 2022 at 09:24:47PM +0800, Jisheng Zhang wrote:
> Add Jisheng Zhang as Bouffalolab SoC maintainer.
>
> Signed-off-by: Jisheng Zhang <jszhang@...nel.org>
> ---
> MAINTAINERS | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 00ff4a2949b8..a6b04249853c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -17729,6 +17729,15 @@ F: arch/riscv/
> N: riscv
> K: riscv
>
> +RISC-V BOUFFALOLAB SOC SUPPORT
> +M: Jisheng Zhang <jszhang@...nel.org>
> +L: linux-riscv@...ts.infradead.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/riscv/bouffalolab.yaml
> +F: Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml
> +F: arch/riscv/boot/dts/bouffalolab/
> +F: drivers/tty/serial/bflb_uart.c
I think I asked last time but I didn't see an answer on lore or my
mailbox - if you intend sending Arnd PRs for this stuff, please add a
git tree here. Otherwise, LMK and I'll bundle it with the other "misc
riscv devicetree" stuff.
Thanks,
Conor.
> RISC-V MICROCHIP FPGA SUPPORT
> M: Conor Dooley <conor.dooley@...rochip.com>
> M: Daire McNamara <daire.mcnamara@...rochip.com>
> --
> 2.38.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@...ts.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
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