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Message-Id: <20221128164147.158441-1-nathan.morrison@timesys.com>
Date: Mon, 28 Nov 2022 11:41:47 -0500
From: Nathan Barrett-Morrison <nathan.morrison@...esys.com>
To: unlisted-recipients:; (no To-header on input)
Cc: nathan.morrison@...esys.com, greg.malysa@...esys.com,
Mark Brown <broonie@...nel.org>,
linux-spi@...r.kernel.org (open list:SPI SUBSYSTEM),
linux-kernel@...r.kernel.org (open list)
Subject: [PATCH] spi: cadence-quadspi: Add minimum operable clock rate warning to baudrate divisor calculation
This Cadence QSPI IP has a 4-bit clock divisor field
for baud rate division. For example:
0b0000 = /2
0b0001 = /4
0b0010 = /6
...
0b1111 = /32
The maximum divisor is 32
(when div = CQSPI_REG_CONFIG_BAUD_MASK).
If we assume a reference clock of 500MHz and we set
our spi-max-frequency to something low, such as 10 MHz.
The calculated bit field for the divisor ends up being:
DIV_ROUND_UP(500000000/(2*10000000))-1 = 25
25 is 0b11001... which truncates to a divisor field of 0b1001 (or /20).
This is higher than our anticipated max-frequency of 10MHz
(500MHz/20 = 25 MHz). Instead, let's make sure we're always using
the maximum divisor (/32) in this case and give the user a warning about
the rate adjustment.
Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@...esys.com>
---
drivers/spi/spi-cadence-quadspi.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 447230547945..21b60b354404 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1119,6 +1119,14 @@ static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
/* Recalculate the baudrate divisor based on QSPI specification. */
div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
+ /* Maximum baud divisor */
+ if (div > CQSPI_REG_CONFIG_BAUD_MASK) {
+ div = CQSPI_REG_CONFIG_BAUD_MASK;
+ dev_warn(&cqspi->pdev->dev,
+ "Unable to adjust clock <= %d hz. Reduced to %d hz\n",
+ cqspi->sclk, ref_clk_hz/((div+1)*2));
+ }
+
reg = readl(reg_base + CQSPI_REG_CONFIG);
reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
--
2.30.2
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