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Message-ID: <417a6fb6-6ae7-a2bf-c549-fdba6e5765f6@alliedtelesis.co.nz>
Date: Mon, 28 Nov 2022 20:24:40 +0000
From: Chris Packham <Chris.Packham@...iedtelesis.co.nz>
To: Pali Rohár <pali@...nel.org>,
Thierry Reding <thierry.reding@...il.com>,
Uwe Kleine-König
<u.kleine-koenig@...gutronix.de>, Lee Jones <lee.jones@...aro.org>,
"Linus Walleij" <linus.walleij@...aro.org>,
Bartosz Golaszewski <brgl@...ev.pl>,
"Rob Herring" <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Andrew Lunn <andrew@...n.ch>,
"Gregory Clement" <gregory.clement@...tlin.com>,
Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
Marek Behún <kabel@...nel.org>
CC: "linux-pwm@...r.kernel.org" <linux-pwm@...r.kernel.org>,
"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v2 3/4] ARM: dts: armada-38x: Fix compatible string for
gpios
Hi Pali,
On 15/07/22 06:33, Pali Rohár wrote:
> Armada 38x supports per CPU interrupts for gpios, like Armada XP. Pre-XP
> variants like Armada 370 do not support per CPU interrupts for gpios.
>
> So change compatible string for Armada 38x from "marvell,armada-370-gpio"
> which indicates pre-XP variant to "marvell,armadaxp-gpio" which indicates
> XP variant or new.
>
> Driver gpio-mvebu.c which handles both pre-XP and XP variants already
> provides support for per CPU interrupts on XP and newer variants.
>
> Signed-off-by: Pali Rohár <pali@...nel.org>
> Fixes: 7cb2acb3fbae ("ARM: dts: mvebu: Add PWM properties for armada-38x")
> ---
> arch/arm/boot/dts/armada-38x.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
> index df3c8d1d8f64..9343de6947b3 100644
> --- a/arch/arm/boot/dts/armada-38x.dtsi
> +++ b/arch/arm/boot/dts/armada-38x.dtsi
> @@ -292,7 +292,7 @@
> };
>
> gpio0: gpio@...00 {
> - compatible = "marvell,armada-370-gpio",
> + compatible = "marvell,armadaxp-gpio",
> "marvell,orion-gpio";
> reg = <0x18100 0x40>, <0x181c0 0x08>;
> reg-names = "gpio", "pwm";
Currently when you specify the "marvell,armadaxp-gpio" compatible this
causes the driver to expect the 2nd reg property to be the per-CPU
interrupt registers. The code in question is
/*
* The Armada XP has a second range of registers for the
* per-CPU registers
*/
if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
base = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(base))
return PTR_ERR(base);
mvchip->percpu_regs =
devm_regmap_init_mmio(&pdev->dev, base,
&mvebu_gpio_regmap_config);
if (IS_ERR(mvchip->percpu_regs))
return PTR_ERR(mvchip->percpu_regs);
}
But with your code change resource[1] is pointing at the blink enable
register not at the per-CPU interrupt register (offset 18800/18840).
> @@ -310,7 +310,7 @@
> };
>
> gpio1: gpio@...40 {
> - compatible = "marvell,armada-370-gpio",
> + compatible = "marvell,armadaxp-gpio",
> "marvell,orion-gpio";
> reg = <0x18140 0x40>, <0x181c8 0x08>;
> reg-names = "gpio", "pwm";
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