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Message-ID: <Y4VJbfxwk2zQhkf5@google.com>
Date: Mon, 28 Nov 2022 23:51:09 +0000
From: Sean Christopherson <seanjc@...gle.com>
To: Isaku Yamahata <isaku.yamahata@...il.com>
Cc: "Huang, Kai" <kai.huang@...el.com>,
"kvm@...r.kernel.org" <kvm@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"Yamahata, Isaku" <isaku.yamahata@...el.com>,
"pbonzini@...hat.com" <pbonzini@...hat.com>,
"Shahar, Sagi" <sagis@...gle.com>,
"Aktas, Erdem" <erdemaktas@...gle.com>,
"dmatlack@...gle.com" <dmatlack@...gle.com>
Subject: Re: [PATCH v10 034/108] KVM: x86/mmu: Add Suppress VE bit to
shadow_mmio_{value, mask}
On Thu, Nov 17, 2022, Isaku Yamahata wrote:
> On Wed, Nov 09, 2022 at 11:48:30AM +0000,
> "Huang, Kai" <kai.huang@...el.com> wrote:
>
> > On Sat, 2022-10-29 at 23:22 -0700, isaku.yamahata@...el.com wrote:
> > > From: Isaku Yamahata <isaku.yamahata@...el.com>
> > >
> > > Because TDX will need shadow_mmio_mask to be VMX_SUPPRESS_VE | RWX
> > > shadow_mmio_value to be 0, make VMX EPT case use same value for TDX
> > > shadow_mmio_mask.
> > >
> >
> > TDX need to use different mmio_mask/value doesn't mean they need to be changed
> > for VMX guest. I think the true purpose here is to still be able to use a
> > global shadow_mmio_mask for both TDX and VMX guests. So please explicitly call
> > out.
>
> That's right. With this change, per-VM shadow_mmio_{value, mask} can be avoided.
> The common value can be used for both VMX and TDX.
No, the mask can be global, but the value needs to be per-VM. VMX needs to
generate an EPT misconfig, but TDX needs to generate an EPT violation to get the
automagic #VE reflection.
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