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Message-ID: <Y4TLMLKDG5SVNoJ7@wendy>
Date: Mon, 28 Nov 2022 14:52:32 +0000
From: Conor Dooley <conor.dooley@...rochip.com>
To: Icenowy Zheng <uwu@...nowy.me>
CC: Conor Dooley <conor@...nel.org>,
Jisheng Zhang <jszhang@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jiri Slaby <jirislaby@...nel.org>,
Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>,
<linux-riscv@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-serial@...r.kernel.org>
Subject: Re: [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base
device tree
On Mon, Nov 28, 2022 at 05:52:51PM +0800, Icenowy Zheng wrote:
> 在 2022-11-27星期日的 17:21 +0000,Conor Dooley写道:
> > +CC Icenowy
> >
> > On Sun, Nov 27, 2022 at 09:24:45PM +0800, Jisheng Zhang wrote:
> > > Add a baisc dtsi for the bouffalolab bl808 SoC.
> > >
> > > Signed-off-by: Jisheng Zhang <jszhang@...nel.org>
> > > ---
> > > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74
> > > + plic: interrupt-controller@...00000 {
> > > + compatible = "thead,c900-plic";
> >
> > Hmm, @Icenowy - should this use your new open-c906-plic compatible
> > from
> > 20221121041757.418645-4-uwu@...nowy.me ?
>
> I am against using openc906-plic.
>
> Maybe I will add "thead,c906-plic", "thead,c900-plic" as an valid
> compatible, as there seems to be few options related to PLIC/CLINT for
> C906/C910 (at least as the open document of them say).
You two know this a lot better than I do, I'll leave it up to you two to
sort out :) Either way, we need something changed here to satisfy the
bindings.
> > As is, dtbs_check gives a:
> > bl808-sipeed-m1s-dock.dtb: interrupt-controller@...00000: compatible:
> > 'oneOf' conditional failed, one must be fixed:
> > ['thead,c900-plic'] is too short
> >
> > > + reg = <0xe0000000 0x4000000>;
> > > + interrupts-extended = <&cpu0_intc
> > > 0xffffffff>,
> > > + <&cpu0_intc 9>;
> > > + interrupt-controller;
> > > + #address-cells = <0>;
> > > + #interrupt-cells = <2>;
> > > + riscv,ndev = <64>;
> > > + };
> > > + };
> > > +};
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