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Date: Tue, 29 Nov 2022 15:04:01 +0800
From: Chen-Yu Tsai <wenst@...omium.org>
To: sboyd@...nel.org, robh+dt@...nel.org,
angelogioacchino.delregno@...labora.com, johnson.wang@...iatek.com,
krzysztof.kozlowski+dt@...aro.org
Cc: linux-clk@...r.kernel.org,
Project_Global_Chrome_Upstream_Group@...iatek.com,
linux-mediatek@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 0/4] Introduce MediaTek frequency hopping driver
On Mon, 21 Nov 2022 20:29:53 +0800, Johnson Wang wrote:
> The purpose of this serie is to enhance frequency hopping and spread spectrum
> clocking feature for MT8186.
> We introduce new PLL register APIs and some helpers for FHCTL hardware control.
> For MT8186 PLL driver, we replace mtk_clk_register_plls() with newly added API
> to support frequency hopping and SSC function for specific PLLs.
>
> Changes in v5:
> - Add the reviewed-by tags.
> - Move binding document to bindings/clock folder.
> - change some coding style in clk-pllfh.c
>
> [...]
Applied, thanks!
[1/4] clk: mediatek: Export PLL operations symbols
commit: 029c936ae7e14ce49d043527087abb5f4b0ea48c
[2/4] dt-bindings: clock: mediatek: Add new bindings of MediaTek frequency hopping
commit: cfcefe36bf939107eeba7b1114e3d82e31f92893
[3/4] clk: mediatek: Add new clock driver to handle FHCTL hardware
commit: d7964de8a8ea800910fdd4e365c42a9e7d5c54aa
[4/4] clk: mediatek: Change PLL register API for MT8186
commit: 633e34d0f46ed36f1de15ede00e4b31f4d7cccae
Best regards,
--
Chen-Yu Tsai <wenst@...omium.org>
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