linux-kernel - Re: [PATCH] x86/boot: Remove x86

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Date:   Tue, 29 Nov 2022 09:50:25 +0100
From:   Uros Bizjak <ubizjak@...il.com>
To:     Borislav Petkov <bp@...en8.de>
Cc:     x86@...nel.org, linux-kernel@...r.kernel.org,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        "H. Peter Anvin" <hpa@...or.com>
Subject: Re: [PATCH] x86/boot: Remove x86_32 PIC using ebx workaround

On Tue, Nov 29, 2022 at 9:31 AM Borislav Petkov <bp@...en8.de> wrote:
>
> On Tue, Nov 29, 2022 at 08:39:23AM +0100, Uros Bizjak wrote:
> > On Mon, Nov 28, 2022 at 11:20 PM Borislav Petkov <bp@...en8.de> wrote:
> > >
> > > On Fri, Nov 04, 2022 at 01:45:46PM +0100, Uros Bizjak wrote:
> > > > Current minimum required version of GCC is version 5.1 which allows
> > > > reuse of PIC hard register on x86/x86-64 targets [1]. Remove
> > > > obsolete workaround that was needed for earlier GCC versions.
> > > >
> > > > [1] https://gcc.gnu.org/gcc-5/changes.html
> > >
> > > Thanks for the doc pointer.
> > >
> > > Lemme see if I understand this commit message correctly:
> > >
> > > SysV i386 ABI says that %ebx is used as the base reg in PIC. gcc 5 and
> > > newer can handle all possible cases properly where inline asm could
> > > clobber the PIC reg. I.e., it is able to deal with the "=b" constraint
> > > where an insn can overwrite %ebx and it'll push and pop around that
> > > statement.
> >
> > gcc-5 considers PIC register as a pseudo-register and reloads it
>
> So not a "hard" register as you say above?

There are registers of different "hardness" as far as gcc is
concerned. Before gcc-5.1, PIC register was considered as "fixed", it
was simply unavailable to a register allocator, decreasing the
miniscule available x86_32 register set by one register. Also, RA was
unable to satisfy the "=b" constraint. OTOH, a pseudo register belongs
to a certain class of registers (e.g. integer registers) and when
allocating real ("hard" ) registers, RA uses instruction (or inline
asm) register constraints to allocate correct "hard" register. In this
aspect, PIC access "requires" %ebx register in the same way as e.g.
shift instructions "require" %cl register. gcc-5.1 allows RA much more
freedom of how to use %ebx register - it can be used for other
purposes , as long as it is reloaded with correct value before insn
with PIC access.

> > x86_64 does not use PIC register for small code models. Also, it uses
> > %r15 instead of %rbx for PIC register, so the removed workaround
> > applies only to x86_32.
>
> Let's see:
>
> arch/x86/Makefile:
>         # Never want PIC in a 32-bit kernel, prevent breakage with GCC built
>         # with nonstandard options
>         KBUILD_CFLAGS += -fno-pic
>
> $ gcc -Wp,-MMD,arch/x86/boot/.cpuflags.o.d ... -fno-pic ... -D__KBUILD_MODNAME=kmod_cpuflags -c -o arch/x86/boot/cpuflags.o arch/x86/boot/cpuflags.c
>
> So this workaround applies to nothing, I'd say. :)

It looks like the workaround serves no purpose even when compiled with
gcc < 5.1.

Uros.