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Date: Tue, 29 Nov 2022 12:36:53 +0100
From: Ulf Hansson <ulf.hansson@...aro.org>
To: Hector Martin <marcan@...can.st>
Cc: "Rafael J. Wysocki" <rafael@...nel.org>,
Viresh Kumar <viresh.kumar@...aro.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Sven Peter <sven@...npeter.dev>,
Alyssa Rosenzweig <alyssa@...enzweig.io>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Stephen Boyd <sboyd@...nel.org>, Marc Zyngier <maz@...nel.org>,
Mark Kettenis <mark.kettenis@...all.nl>, asahi@...ts.linux.dev,
linux-arm-kernel@...ts.infradead.org, linux-pm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 2/4] dt-bindings: cpufreq: apple,soc-cpufreq: Add
binding for Apple SoC cpufreq
On Mon, 28 Nov 2022 at 15:29, Hector Martin <marcan@...can.st> wrote:
>
> This binding represents the cpufreq/DVFS hardware present in Apple SoCs.
> The hardware has an independent controller per CPU cluster, and we
> represent them as unique nodes in order to accurately describe the
> hardware. The driver is responsible for binding them as a single cpufreq
> device (in the Linux cpufreq model).
>
> Acked-by: Marc Zyngier <maz@...nel.org>
> Signed-off-by: Hector Martin <marcan@...can.st>
> ---
> .../cpufreq/apple,cluster-cpufreq.yaml | 117 ++++++++++++++++++
> 1 file changed, 117 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/cpufreq/apple,cluster-cpufreq.yaml
>
> diff --git a/Documentation/devicetree/bindings/cpufreq/apple,cluster-cpufreq.yaml b/Documentation/devicetree/bindings/cpufreq/apple,cluster-cpufreq.yaml
> new file mode 100644
> index 000000000000..76cb9726660e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/cpufreq/apple,cluster-cpufreq.yaml
> @@ -0,0 +1,117 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/cpufreq/apple,cluster-cpufreq.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Apple SoC cluster cpufreq device
> +
> +maintainers:
> + - Hector Martin <marcan@...can.st>
> +
> +description: |
> + Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of
> + the cluster management register block. This binding uses the standard
> + operating-points-v2 table to define the CPU performance states, with the
> + opp-level property specifying the hardware p-state index for that level.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - apple,t8103-cluster-cpufreq
> + - apple,t8112-cluster-cpufreq
> + - const: apple,cluster-cpufreq
> + - items:
> + - const: apple,t6000-cluster-cpufreq
> + - const: apple,t8103-cluster-cpufreq
> + - const: apple,cluster-cpufreq
> +
> + reg:
> + maxItems: 1
> +
> + '#performance-domain-cells':
> + const: 0
> +
> +required:
> + - compatible
> + - reg
> + - '#performance-domain-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + // This example shows a single CPU per domain and 2 domains,
> + // with two p-states per domain.
> + // Shipping hardware has 2-4 CPUs per domain and 2-6 domains.
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "apple,icestorm";
> + device_type = "cpu";
> + reg = <0x0 0x0>;
> + operating-points-v2 = <&ecluster_opp>;
To me, it looks like the operating-points-v2 phandle better belongs in
the performance-domains provider node. I mean, isn't the OPPs really a
description of the performance-domain provider?
That said, I suggest we try to extend the generic performance-domain
binding [1] with an "operating-points-v2". In that way, we should
instead be able to reference it from this binding.
In fact, that would be very similar to what already exists for the
generic power-domain binding [2]. I think it would be rather nice to
follow a similar pattern for the performance-domain binding.
> + performance-domains = <&cpufreq_e>;
> + };
> +
> + cpu@...00 {
> + compatible = "apple,firestorm";
> + device_type = "cpu";
> + reg = <0x0 0x10100>;
> + operating-points-v2 = <&pcluster_opp>;
> + performance-domains = <&cpufreq_p>;
> + };
> + };
> +
> + ecluster_opp: opp-table-0 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp01 {
> + opp-hz = /bits/ 64 <600000000>;
> + opp-level = <1>;
> + clock-latency-ns = <7500>;
> + };
> + opp02 {
> + opp-hz = /bits/ 64 <972000000>;
> + opp-level = <2>;
> + clock-latency-ns = <22000>;
> + };
> + };
> +
> + pcluster_opp: opp-table-1 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp01 {
> + opp-hz = /bits/ 64 <600000000>;
> + opp-level = <1>;
> + clock-latency-ns = <8000>;
> + };
> + opp02 {
> + opp-hz = /bits/ 64 <828000000>;
> + opp-level = <2>;
> + clock-latency-ns = <19000>;
> + };
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpufreq_e: performance-controller@...e20000 {
> + compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
> + reg = <0x2 0x10e20000 0 0x1000>;
> + #performance-domain-cells = <0>;
> + };
> +
> + cpufreq_p: performance-controller@...e20000 {
> + compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
> + reg = <0x2 0x11e20000 0 0x1000>;
> + #performance-domain-cells = <0>;
> + };
> + };
Kind regards
Uffe
[1]
Documentation/devicetree/bindings/dvfs/performance-domain.yaml
[2]
Documentation/devicetree/bindings/power/power-domain.yaml
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