linux-kernel - [PATCH v2 1/2] dt-bindings: riscv: fix underscore requirement for addtional standard extensions

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Message-Id: <20221130180422.1642652-2-conor@kernel.org>
Date:   Wed, 30 Nov 2022 18:04:22 +0000
From:   Conor Dooley <conor@...nel.org>
To:     Palmer Dabbelt <palmer@...belt.com>,
        linux-riscv@...ts.infradead.org
Cc:     Conor Dooley <conor.dooley@...rochip.com>,
        Conor Dooley <conor@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Heiko Stuebner <heiko@...ech.de>,
        Andrew Jones <ajones@...tanamicro.com>,
        Guo Ren <guoren@...nel.org>, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: [PATCH v2 1/2] dt-bindings: riscv: fix underscore requirement for addtional standard extensions

From: Conor Dooley <conor.dooley@...rochip.com>

The RISC-V ISA Manual allows for the first Additional Standard
Extension having no leading underscore. Only if there are multiple
Additional Standard Extensions is it needed to have an underscore.

The dt-binding does not validate that a multi-letter extension is
canonically ordered, as that'd need an even worse regex than is here,
but it should not fail validation for valid ISA strings.

Allow the first Z multi-letter extension to appear immediately prior
after the single-letter extensions.

Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5
Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")
Acked-by: Guo Ren <guoren@...nel.org>
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 90a7cabf58fe..e80c967a4fa4 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -80,7 +80,7 @@ properties:
       insensitive, letters in the riscv,isa string must be all
       lowercase to simplify parsing.
     $ref: "/schemas/types.yaml#/definitions/string"
-    pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$
+    pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
 
   # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
   timebase-frequency: false
-- 
2.38.1