linux-kernel - [PATCH 5/6] dt-bindings: crypto: Add bindings for Starfive crypto driver

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Message-ID: <20221130055214.2416888-6-jiajie.ho@starfivetech.com>
Date:   Wed, 30 Nov 2022 13:52:13 +0800
From:   Jia Jie Ho <jiajie.ho@...rfivetech.com>
To:     Herbert Xu <herbert@...dor.apana.org.au>,
        "David S . Miller" <davem@...emloft.net>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
CC:     <linux-crypto@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
        Jia Jie Ho <jiajie.ho@...rfivetech.com>
Subject: [PATCH 5/6] dt-bindings: crypto: Add bindings for Starfive crypto driver

Add documentation to describe Starfive crypto
driver bindings.

Signed-off-by: Jia Jie Ho <jiajie.ho@...rfivetech.com>
Signed-off-by: Huan Feng <huan.feng@...rfivetech.com>
---
 .../bindings/crypto/starfive-crypto.yaml      | 109 ++++++++++++++++++
 1 file changed, 109 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/starfive-crypto.yaml

diff --git a/Documentation/devicetree/bindings/crypto/starfive-crypto.yaml b/Documentation/devicetree/bindings/crypto/starfive-crypto.yaml
new file mode 100644
index 000000000000..6b852f774c32
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/starfive-crypto.yaml
@@ -0,0 +1,109 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/starfive-crypto.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive Crypto Controller Device Tree Bindings
+
+maintainers:
+  - Jia Jie Ho <jiajie.ho@...rfivetech.com>
+  - William Qiu <william.qiu@...rfivetech.com>
+
+properties:
+  compatible:
+    const: starfive,jh7110-crypto
+
+  reg:
+    maxItems: 1
+
+  reg-names:
+    items:
+      - const: secreg
+
+  clocks:
+    items:
+      - description: Hardware reference clock
+      - description: AHB reference clock
+
+  clock-names:
+    items:
+      - const: sec_hclk
+      - const: sec_ahb
+
+  interrupts:
+    items:
+      - description: Interrupt pin for algo completion
+      - description: Interrupt pin for DMA transfer completion
+
+  interrupt-names:
+    items:
+      - const: secirq
+      - const: dmairq
+
+  resets:
+    items:
+      - description: STG domain reset line
+
+  reset-names:
+    items:
+      - const: sec_hre
+
+  enable-side-channel-mitigation:
+    description: Enable side-channel-mitigation feature for AES module.
+        Enabling this feature will affect the speed performance of
+        crypto engine.
+    type: boolean
+
+  enable-dma:
+    description: Enable data transfer using dedicated DMA controller.
+    type: boolean
+
+  dmas:
+    items:
+      - description: TX DMA channel
+      - description: RX DMA channel
+
+  dma-names:
+    items:
+      - const: sec_m
+      - const: sec_p
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive-jh7110.h>
+    #include <dt-bindings/reset/starfive-jh7110.h>
+
+    soc {
+            #address-cells = <2>;
+            #size-cells = <2>;
+
+            crypto: crypto@...00000 {
+                    compatible = "starfive,jh7110-crypto";
+                    reg = <0x0 0x16000000 0x0 0x4000>;
+                    reg-names = "secreg";
+                    clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
+                    <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
+                    interrupts = <28>, <29>;
+                    interrupt-names = "secirq", "dmairq";
+                    clock-names = "sec_hclk","sec_ahb";
+                    resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
+                    reset-names = "sec_hre";
+                    enable-side-channel-mitigation;
+                    enable-dma;
+                    dmas = <&sec_dma 1 2>,
+                           <&sec_dma 0 2>;
+                    dma-names = "sec_m","sec_p";
+            };
+    };
-- 
2.25.1