[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <87h6yg1xlo.fsf@all.your.base.are.belong.to.us>
Date: Wed, 30 Nov 2022 12:38:11 +0100
From: Björn Töpel <bjorn@...nel.org>
To: Pu Lehui <pulehui@...weicloud.com>, bpf@...r.kernel.org,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Cc: Alexei Starovoitov <ast@...nel.org>,
Daniel Borkmann <daniel@...earbox.net>,
Andrii Nakryiko <andrii@...nel.org>,
Martin KaFai Lau <martin.lau@...ux.dev>,
Song Liu <song@...nel.org>, Yonghong Song <yhs@...com>,
John Fastabend <john.fastabend@...il.com>,
KP Singh <kpsingh@...nel.org>,
Stanislav Fomichev <sdf@...gle.com>,
Hao Luo <haoluo@...gle.com>, Jiri Olsa <jolsa@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Pu Lehui <pulehui@...wei.com>,
Pu Lehui <pulehui@...weicloud.com>
Subject: Re: [PATCH bpf] riscv, bpf: Emit fixed-length imm64 for
BPF_PSEUDO_FUNC
Pu Lehui <pulehui@...weicloud.com> writes:
> From: Pu Lehui <pulehui@...wei.com>
>
> For BPF_PSEUDO_FUNC instruction, verifier will refill imm with
> correct addresses of bpf_calls and then run last pass of JIT.
> Since the emit_imm of RV64 is variable-length, which will emit
> appropriate length instructions accorroding to the imm, it may
> broke ctx->offset, and lead to unpredictable problem, such as
> inaccurate jump. So let's fix it with fixed-length imm64 insns.
Ah, nice one! So, the the invariant doesn't hold (the image grow in the
last pass).
> Fixes: 69c087ba6225 ("bpf: Add bpf_for_each_map_elem() helper")
This is odd? This can't be the right Fixes-tag...
> Signed-off-by: Pu Lehui <pulehui@...wei.com>
> ---
> arch/riscv/net/bpf_jit_comp64.c | 31 ++++++++++++++++++++++++++++++-
> 1 file changed, 30 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
> index eb99df41fa33..f984d5fa014b 100644
> --- a/arch/riscv/net/bpf_jit_comp64.c
> +++ b/arch/riscv/net/bpf_jit_comp64.c
> @@ -139,6 +139,30 @@ static bool in_auipc_jalr_range(s64 val)
> val < ((1L << 31) - (1L << 11));
> }
>
> +/* Emit fixed-length instructions for 32-bit imm */
> +static void emit_fixed_imm32(u8 rd, s32 val, struct rv_jit_context *ctx)
> +{
> + s32 upper = (val + (1U << 11)) >> 12;
> + s32 lower = ((val & 0xfff) << 20) >> 20;
> +
> + emit(rv_lui(rd, upper), ctx);
> + emit(rv_addi(rd, rd, lower), ctx);
> +}
> +
> +/* Emit fixed-length instructions for 64-bit imm */
> +static void emit_fixed_imm64(u8 rd, s64 val, struct rv_jit_context *ctx)
> +{
> + /* Compensation for sign-extension of rv_addi */
> + s32 imm_hi = (val + (1U << 31)) >> 32;
> + s32 imm_lo = val;
> +
> + emit_fixed_imm32(rd, imm_hi, ctx);
> + emit_fixed_imm32(RV_REG_T1, imm_lo, ctx);
> + emit(rv_slli(rd, rd, 32), ctx);
> + emit(rv_add(rd, rd, RV_REG_T1), ctx);
> +}
Hmm, will this really be fixed? We can end up with compressed
instructions, which can then be a non-compressed in the last pass, and
we have the same problem?
The range of valid address for RV64 (sv39 to sv57) are
0xffffffff00000000 to 0xffffffffffffffff, so I think we can do better
than 6 insn, no? My gut feeling (I need to tinker a bit) is that 4
should be sufficient.
Note that worst case for a imm64 load are 8 instructions, but this is
not the general case.
Björn
Powered by blists - more mailing lists