| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Wed, 30 Nov 2022 13:59:00 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Abel Vesa <abel.vesa@...aro.org>
Cc: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Mike Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-clk@...r.kernel.org
Subject: Re: [PATCH v4 8/9] clk: qcom: rpmh: Add support for SM8550 rpmh clocks
On Wed, 30 Nov 2022 at 13:45, Dmitry Baryshkov
<dmitry.baryshkov@...aro.org> wrote:
>
> On Wed, 30 Nov 2022 at 13:30, Abel Vesa <abel.vesa@...aro.org> wrote:
> >
> > Adds the RPMH clocks present in SM8550 SoC.
> >
> > Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
> > Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
> > ---
> > drivers/clk/qcom/clk-rpmh.c | 110 +++++++++++++++++++++++++++++-------
> > 1 file changed, 90 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
> > index 0471bab82464..3204df3fda86 100644
> > --- a/drivers/clk/qcom/clk-rpmh.c
> > +++ b/drivers/clk/qcom/clk-rpmh.c
> > @@ -132,6 +132,36 @@ static DEFINE_MUTEX(rpmh_clk_lock);
> > }, \
> > }
> >
> > +#define DEFINE_CLK_RPMH_FIXED(_platform, _name, _name_active, \
> > + _parent_name, _name_active_parent, \
> > + _div) \
> > + static struct clk_fixed_factor _platform##_##_name = { \
> > + .mult = 1, \
> > + .div = _div, \
> > + .hw.init = &(struct clk_init_data){ \
> > + .ops = &clk_fixed_factor_ops, \
> > + .name = #_name, \
> > + .parent_data = &(const struct clk_parent_data){ \
> > + .fw_name = #_parent_name, \
> > + .name = #_parent_name, \
> > + }, \
> > + .num_parents = 1, \
> > + }, \
> > + }; \
> > + static struct clk_fixed_factor _platform##_##_name_active = { \
> > + .mult = 1, \
> > + .div = _div, \
> > + .hw.init = &(struct clk_init_data){ \
> > + .ops = &clk_fixed_factor_ops, \
> > + .name = #_name_active, \
> > + .parent_data = &(const struct clk_parent_data){ \
> > + .fw_name = #_name_active_parent,\
> > + .name = #_name_active_parent, \
> > + }, \
> > + .num_parents = 1, \
> > + }, \
> > + }
> > +
>
> Please use CLK_FIXED_FACTOR_FW_NAME() instead.
Or even better CLK_FIXED_FACTOR_HW(). It fits better here.
>
> > static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw)
> > {
> > return container_of(_hw, struct clk_rpmh, hw);
> > @@ -579,6 +609,43 @@ static const struct clk_rpmh_desc clk_rpmh_sm8450 = {
> > .num_clks = ARRAY_SIZE(sm8450_rpmh_clocks),
> > };
> >
> > +DEFINE_CLK_RPMH_ARC(sm8550, xo_pad, xo_pad_ao, "xo.lvl", 0x03, 2);
> > +DEFINE_CLK_RPMH_FIXED(sm8550, bi_tcxo, bi_tcxo_ao, xo_pad, xo_pad_ao, 2);
> > +DEFINE_CLK_RPMH_VRM(sm8550, rf_clk1, rf_clk1_ao, "clka1", 1);
> > +DEFINE_CLK_RPMH_VRM(sm8550, rf_clk2, rf_clk2_ao, "clka2", 1);
> > +DEFINE_CLK_RPMH_VRM(sm8550, rf_clk3, rf_clk3_ao, "clka3", 1);
> > +DEFINE_CLK_RPMH_VRM(sm8550, rf_clk4, rf_clk4_ao, "clka4", 1);
> > +DEFINE_CLK_RPMH_VRM(sm8550, ln_bb_clk1, ln_bb_clk1_ao, "clka6", 2);
> > +DEFINE_CLK_RPMH_VRM(sm8550, ln_bb_clk2, ln_bb_clk2_ao, "clka7", 2);
> > +DEFINE_CLK_RPMH_VRM(sm8550, ln_bb_clk3, ln_bb_clk3_ao, "clka8", 2);
> > +
> > +static struct clk_hw *sm8550_rpmh_clocks[] = {
> > + [RPMH_CXO_PAD_CLK] = &sm8550_xo_pad.hw,
> > + [RPMH_CXO_PAD_CLK_A] = &sm8550_xo_pad_ao.hw,
> > + [RPMH_CXO_CLK] = &sm8550_bi_tcxo.hw,
> > + [RPMH_CXO_CLK_A] = &sm8550_bi_tcxo_ao.hw,
> > + [RPMH_LN_BB_CLK1] = &sm8550_ln_bb_clk1.hw,
> > + [RPMH_LN_BB_CLK1_A] = &sm8550_ln_bb_clk1_ao.hw,
> > + [RPMH_LN_BB_CLK2] = &sm8550_ln_bb_clk2.hw,
> > + [RPMH_LN_BB_CLK2_A] = &sm8550_ln_bb_clk2_ao.hw,
> > + [RPMH_LN_BB_CLK3] = &sm8550_ln_bb_clk3.hw,
> > + [RPMH_LN_BB_CLK3_A] = &sm8550_ln_bb_clk3_ao.hw,
> > + [RPMH_RF_CLK1] = &sm8550_rf_clk1.hw,
> > + [RPMH_RF_CLK1_A] = &sm8550_rf_clk1_ao.hw,
> > + [RPMH_RF_CLK2] = &sm8550_rf_clk2.hw,
> > + [RPMH_RF_CLK2_A] = &sm8550_rf_clk2_ao.hw,
> > + [RPMH_RF_CLK3] = &sm8550_rf_clk3.hw,
> > + [RPMH_RF_CLK3_A] = &sm8550_rf_clk3_ao.hw,
> > + [RPMH_RF_CLK4] = &sm8550_rf_clk4.hw,
> > + [RPMH_RF_CLK4_A] = &sm8550_rf_clk4_ao.hw,
> > + [RPMH_IPA_CLK] = &sdm845_ipa.hw,
> > +};
> > +
> > +static const struct clk_rpmh_desc clk_rpmh_sm8550 = {
> > + .clks = sm8550_rpmh_clocks,
> > + .num_clks = ARRAY_SIZE(sm8550_rpmh_clocks),
> > +};
> > +
> > static struct clk_hw *sc7280_rpmh_clocks[] = {
> > [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
> > [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
> > @@ -682,29 +749,31 @@ static int clk_rpmh_probe(struct platform_device *pdev)
> >
> > name = hw_clks[i]->init->name;
> >
> > - rpmh_clk = to_clk_rpmh(hw_clks[i]);
> > - res_addr = cmd_db_read_addr(rpmh_clk->res_name);
> > - if (!res_addr) {
> > - dev_err(&pdev->dev, "missing RPMh resource address for %s\n",
> > - rpmh_clk->res_name);
> > - return -ENODEV;
> > - }
> > + if (hw_clks[i]->init->ops != &clk_fixed_factor_ops) {
>
> This looks ugly a bit. I'd rather add something like non_cmd_clks to
> the clk_rpmh_desc data and register them separately. Or even worse,
> you can keep the rpmh as is, with only cmd-db based clocks and add a
> fixed factor clock to the sm8550 dtsi directly. I have a slight
> preference for the former method, but the latter would also work.
After a second thought, I'd withdraw the second method. Just add a
separate array with non-cmd-db clocks.
>
> > + rpmh_clk = to_clk_rpmh(hw_clks[i]);
> > + res_addr = cmd_db_read_addr(rpmh_clk->res_name);
> > + if (!res_addr) {
> > + dev_err(&pdev->dev, "missing RPMh resource address for %s\n",
> > + rpmh_clk->res_name);
> > + return -ENODEV;
> > + }
> >
> > - data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len);
> > - if (IS_ERR(data)) {
> > - ret = PTR_ERR(data);
> > - dev_err(&pdev->dev,
> > - "error reading RPMh aux data for %s (%d)\n",
> > - rpmh_clk->res_name, ret);
> > - return ret;
> > - }
> > + data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len);
> > + if (IS_ERR(data)) {
> > + ret = PTR_ERR(data);
> > + dev_err(&pdev->dev,
> > + "error reading RPMh aux data for %s (%d)\n",
> > + rpmh_clk->res_name, ret);
> > + return ret;
> > + }
> >
> > - /* Convert unit from Khz to Hz */
> > - if (aux_data_len == sizeof(*data))
> > - rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL;
> > + /* Convert unit from Khz to Hz */
> > + if (aux_data_len == sizeof(*data))
> > + rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL;
> >
> > - rpmh_clk->res_addr += res_addr;
> > - rpmh_clk->dev = &pdev->dev;
> > + rpmh_clk->res_addr += res_addr;
> > + rpmh_clk->dev = &pdev->dev;
> > + }
> >
> > ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]);
> > if (ret) {
> > @@ -739,6 +808,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
> > { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
> > { .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350},
> > { .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450},
> > + { .compatible = "qcom,sm8550-rpmh-clk", .data = &clk_rpmh_sm8550},
> > { .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280},
> > { }
> > };
> > --
> > 2.34.1
> >
>
>
> --
> With best wishes
> Dmitry
--
With best wishes
Dmitry
Powered by blists - more mailing lists