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Message-ID: <Y4jpDvXo/uj9ygLR@spud>
Date: Thu, 1 Dec 2022 17:49:02 +0000
From: Conor Dooley <conor@...nel.org>
To: Yanhong Wang <yanhong.wang@...rfivetech.com>
Cc: linux-riscv@...ts.infradead.org, netdev@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
"David S . Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Emil Renner Berthing <kernel@...il.dk>,
Richard Cochran <richardcochran@...il.com>,
Andrew Lunn <andrew@...n.ch>,
Heiner Kallweit <hkallweit1@...il.com>,
Peter Geis <pgwipeout@...il.com>
Subject: Re: [PATCH v1 7/7] riscv: dts: starfive: visionfive-v2: Add phy
delay_chain configuration
On Thu, Dec 01, 2022 at 05:02:42PM +0800, Yanhong Wang wrote:
> Add phy delay_chain configuration to support motorcomm phy driver for
> StarFive VisionFive 2 board.
>
> Signed-off-by: Yanhong Wang <yanhong.wang@...rfivetech.com>
> ---
> .../jh7110-starfive-visionfive-v2.dts | 46 +++++++++++++++++++
> 1 file changed, 46 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
> index c8946cf3a268..2868ef4c74ef 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-v2.dts
> @@ -15,6 +15,8 @@
>
> aliases {
> serial0 = &uart0;
> + ethernet0=&gmac0;
> + ethernet1=&gmac1;
Please match the whitespace usage of the existing entry.
> };
>
> chosen {
> @@ -114,3 +116,47 @@
> pinctrl-0 = <&uart0_pins>;
> status = "okay";
> };
> +
> +&gmac0 {
> + status = "okay";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + phy-handle = <&phy0>;
> + status = "okay";
> + mdio0 {
A line of whitespace before the child nodes too please :)
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dwmac-mdio";
> + phy0: ethernet-phy@0 {
> + reg = <0>;
> + rxc_dly_en = <1>;
> + tx_delay_sel_fe = <5>;
> + tx_delay_sel = <0xa>;
> + tx_inverted_10 = <0x1>;
> + tx_inverted_100 = <0x1>;
> + tx_inverted_1000 = <0x1>;
> + };
> + };
> +};
> +
> +&gmac1 {
> + status = "okay";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + phy-handle = <&phy1>;
> + status = "okay";
> + mdio1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dwmac-mdio";
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + tx_delay_sel_fe = <5>;
> + tx_delay_sel = <0>;
> + rxc_dly_en = <0>;
> + tx_inverted_10 = <0x1>;
> + tx_inverted_100 = <0x1>;
> + tx_inverted_1000 = <0x0>;
> + };
> + };
> +};
> --
> 2.17.1
>
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