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Message-ID: <fd1ca52a-8f2f-0c3a-aefd-3fac380ecdf2@starfivetech.com>
Date: Fri, 2 Dec 2022 10:06:32 +0800
From: Hal Feng <hal.feng@...rfivetech.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
CC: <linux-riscv@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-clk@...r.kernel.org>, Conor Dooley <conor@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Stephen Boyd <sboyd@...nel.org>,
"Michael Turquette" <mturquette@...libre.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Emil Renner Berthing <emil.renner.berthing@...onical.com>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 09/14] dt-bindings: clock: Add StarFive JH7110 system
clock and reset generator
On Thu, 1 Dec 2022 11:21:04 +0100, Krzysztof Kozlowski wrote:
> On 30/11/2022 19:05, Hal Feng wrote:
>> On Wed, 30 Nov 2022 16:19:06 +0100, Krzysztof Kozlowski wrote:
>>> On 30/11/2022 16:12, Hal Feng wrote:
>>>> On Wed, 30 Nov 2022 12:48:30 +0100, Krzysztof Kozlowski wrote:
>>>>> On 30/11/2022 10:47, Hal Feng wrote:
>>>>>> On Fri, 25 Nov 2022 14:41:12 +0800, Hal Feng wrote:
>>>>>>> On Mon, 21 Nov 2022 09:47:08 +0100, Krzysztof Kozlowski wrote:
>>>>>>>> On 18/11/2022 02:06, Hal Feng wrote:
>>>>>>>>> From: Emil Renner Berthing <kernel@...il.dk>
>>>>>>>>>
>>>>>>>>> Add bindings for the system clock and reset generator (SYSCRG) on the
>>>>>>>>> JH7110 RISC-V SoC by StarFive Ltd.
>>>>>>>>>
>>>>>>>>> Signed-off-by: Emil Renner Berthing <kernel@...il.dk>
>>>>>>>>> Signed-off-by: Hal Feng <hal.feng@...rfivetech.com>
>>>>>>>>
>>>>>>>> Binding headers are coming with the file bringing bindings for the
>>>>>>>> device, so you need to squash patches.
>>>>>>>
>>>>>>> As we discussed in patch 7, could I merge patch 7, 8, 9, 10 and add the
>>>>>>> following files in one commit?
>>>>>>>
>>>>>>> include/dt-bindings/clock/starfive,jh7110-crg.h
>>>>>>> include/dt-bindings/reset/starfive,jh7110-crg.h
>>>>>>> Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
>>>>>>> Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
>>>>>>
>>>>>> Hi, Krzysztof,
>>>>>>
>>>>>> Could you please give me some suggestions?
>>>>>
>>>>> You can keep aon and sys split. First add one of them with their own
>>>>> headers. Then add second with their own defines.
>>>>
>>>> You mean split patch 7 and patch 8 into sys part and aon part
>>>> respectively? There are totally five regions (sys/aon/stg/isp/vout)
>>>> for clocks and resets in JH7110. If we do that, there will be 5
>>>> headers for JH7110 in either clock or reset directory finally. Is
>>>> that OK if there are too many headers for just one SoC?
>>>
>>>
>>> Sorry, I lost the track of what patches you have. The comment was -
>>> bindings include both the doc and headers. You want to split some, some
>>> merge, sorry, no clue. I did not propose splitting headers...
>>
>> It's ok. The problem was that the header
>>
>> include/dt-bindings/clock/starfive,jh7110-crg.h
>>
>> was used in both
>>
>> Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
>>
>> and
>>
>> Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml.
>>
>> The same for include/dt-bindings/reset/starfive,jh7110-crg.h.
>> So should I add these four files in one patch?
>
> No. I think I wrote proposed flow of patches:
> 1. syscrg bindings with header
> 2. aoncrg bindings with changes to header
Great. Got it. Thanks a lot!
Best regards,
Hal
>
> Why do you need to merge anything?
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