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Message-ID: <099c5fab-3edc-71ba-ed65-2002ed2427fb@nvidia.com>
Date: Fri, 2 Dec 2022 10:44:55 +0530
From: Manikanta Maddireddy <mmaddireddy@...dia.com>
To: Jon Hunter <jonathanh@...dia.com>, vkoul@...nel.org,
kishon@...nel.org, krzysztof.kozlowski+dt@...aro.org,
thierry.reding@...il.com, vidyas@...dia.com
Cc: linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org, bhelgaas@...gle.com,
lpieralisi@...nel.org, nkristam@...dia.com
Subject: Re: [PATCH 2/3] arm64: tegra: Add uphy lane number and intr in p2u
nodes
On 12/1/2022 3:14 PM, Jon Hunter wrote:
>
> On 24/11/2022 08:35, Manikanta Maddireddy wrote:
>> UPHY lane number is required to exchange lane margin data between P2U
>> and UPHY. Add uphy lane number in p2u device tree nodes.
>>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@...dia.com>
>> ---
>> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 120 +++++++++++++++++++++++
>> 1 file changed, 120 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
>> b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
>> index eaf05ee9acd1..ec8a28a9d380 100644
>> --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
>> +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
>> @@ -1109,6 +1109,11 @@ p2u_hsio_0: phy@...0000 {
>> reg = <0x03e00000 0x10000>;
>> reg-names = "ctl";
>> + interrupts = <0 336 0x04>;
>
>
> Please use definitions and don't hard-code the values apart from the
> interrupt number.
Ack, I will address in V2.
Thanks,
Manikanta
>
> Jon
>
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