linux-kernel - Re: [PATCH 2/3] dt-bindings: timer: sifive,clint: add compatible for OpenC906

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Message-ID: <4ad56fa249a30167844abcedac53d198606511d8.camel@icenowy.me>
Date:   Fri, 02 Dec 2022 14:12:54 +0800
From:   Icenowy Zheng <uwu@...nowy.me>
To:     Conor Dooley <conor@...nel.org>, Rob Herring <robh@...nel.org>
Cc:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        Marc Zyngier <maz@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Jisheng Zhang <jszhang@...nel.org>,
        Samuel Holland <samuel@...lland.org>,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        linux-riscv@...ts.infradead.org
Subject: Re: [PATCH 2/3] dt-bindings: timer: sifive,clint: add compatible
 for OpenC906

在 2022-12-01星期四的 19:18 +0000，Conor Dooley写道：
> On Wed, Nov 30, 2022 at 12:13:30PM -0600, Rob Herring wrote:
> > On Tue, Nov 22, 2022 at 03:41:27PM +0800, Icenowy Zheng wrote:
> > > 
> > > 
> > > 于 2022年11月22日 GMT+08:00 下午3:35:48, Krzysztof Kozlowski
> > > <krzysztof.kozlowski@...aro.org> 写到:
> > > > On 22/11/2022 08:18, Icenowy Zheng wrote:
> > > > > 在 2022-11-21星期一的 11:06 +0100，Krzysztof Kozlowski写道：
> > > > > > On 21/11/2022 05:17, Icenowy Zheng wrote:
> > > > > > > T-Head OpenC906 is a open-source-licensed fixed-
> > > > > > > configuration of
> > > > > > > C906,
> > > > > > > which is now public and able to be integrated.
> > > > > > > 
> > > > > > > Add a compatible for the CLINT shipped as part of
> > > > > > > OpenC906, which
> > > > > > > should
> > > > > > > just be ordinary C9xx CLINT.
> > > > > > > 
> > > > > > > Signed-off-by: Icenowy Zheng <uwu@...nowy.me>
> > > > > > > ---
> > > > > > >  Documentation/devicetree/bindings/timer/sifive,clint.yam
> > > > > > > l | 1 +
> > > > > > >  1 file changed, 1 insertion(+)
> > > > > > > 
> > > > > > > diff --git
> > > > > > > a/Documentation/devicetree/bindings/timer/sifive,clint.ya
> > > > > > > ml
> > > > > > > b/Documentation/devicetree/bindings/timer/sifive,clint.ya
> > > > > > > ml
> > > > > > > index aada6957216c..86703e995e31 100644
> > > > > > > ---
> > > > > > > a/Documentation/devicetree/bindings/timer/sifive,clint.ya
> > > > > > > ml
> > > > > > > +++
> > > > > > > b/Documentation/devicetree/bindings/timer/sifive,clint.ya
> > > > > > > ml
> > > > > > > @@ -35,6 +35,7 @@ properties:
> > > > > > >            - const: sifive,clint0
> > > > > > >        - items:
> > > > > > >            - enum:
> > > > > > > +              - thead,openc906-clint
> > > > > > >                - allwinner,sun20i-d1-clint
> > > > > > 
> > > > > > Add entries sorted alphabetically. This should be squashed
> > > > > > with
> > > > > > previous
> > > > > > patch.
> > > > > 
> > > > > I make it a seperated patch because I think it's a
> > > > > questionable
> > > > > approach.
> > > > > 
> > > > > If you think it's okay, I will just squash it and put it as
> > > > > the second
> > > > > patch in the next iteration, with adding openc906-plic as the
> > > > > first
> > > > > one.
> > > > 
> > > > What is a questionable approach? Why commit msg is not saying
> > > > this?
> > > 
> > > Ah I mentioned it in the cover letter. The problem is just I
> > > doubt whether
> > > binding strings for single SoCs are necessary.
> > 
> > They are.
> > 
> > Unless all the quirks/bugs/features are somehow guaranteed to be
> > exactly 
> > the same as other SoCs sharing the same compatible string, or there
> > is 
> > another mechanism to identify the exact version (e.g. a version 
> > register).
> 
> Icenowy,
> 
> Having thought about this a little - are we not *more* likely to see
> bug/quirk disparity between implementations of the OpenC906 stuff by
> the very nature of being an open-source IP?

It's an open-source edition of a specific version of the commercial IP,
a fixed configuration.

In addition, maybe we can just retrieve the version infomation via a T-
Head custom CPU configuration register, mcpuid. Despite the
implementation of this register is weird -- it contains 7 different
read-only values, with the most significant nibble behaving as an
index.

> 
> Thanks,
> Conor.
>