linux-kernel - Re: [PATCH v5 3/7] soc: amlogic: meson-pwrc: Add NNA power domain for A311D

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Fri, 2 Dec 2022 09:53:21 +0100
From:   Neil Armstrong <neil.armstrong@...aro.org>
To:     Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
        Tomeu Vizoso <tomeu.vizoso@...labora.com>
Cc:     italonicola@...labora.com, Kevin Hilman <khilman@...libre.com>,
        Jerome Brunet <jbrunet@...libre.com>,
        "moderated list:ARM/Amlogic Meson SoC support" 
        <linux-arm-kernel@...ts.infradead.org>,
        "open list:ARM/Amlogic Meson SoC support" 
        <linux-amlogic@...ts.infradead.org>,
        open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v5 3/7] soc: amlogic: meson-pwrc: Add NNA power domain for
 A311D

On 01/12/2022 23:43, Martin Blumenstingl wrote:
> On Thu, Dec 1, 2022 at 11:30 AM Tomeu Vizoso <tomeu.vizoso@...labora.com> wrote:
>>
>> Based on power initialization sequence in downstream driver.
>>
>> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@...labora.com>
>> Reviewed-by: Neil Armstrong <neil.armstrong@...aro.org>
> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
> 
> [...]
>> +static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = {
>> +       { G12A_HHI_NANOQ_MEM_PD_REG0, GENMASK(31, 0) },
>> +       { G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(23, 0) },
> I noticed the discussion in v1 of this series where Neil noted that
> you should change GENMASK(31, 0) to GENMASK(23, 0) (for
> G12A_HHI_NANOQ_MEM_PD_REG1).
> This is all a bit confusing because the S905D3 datasheet mentions that
> the HHI_NANOQ_MEM_PD_REG1 register uses the full 32 bits.
> I'm still fine with the way it is right now because the datasheets are
> not always perfect.

Yes they're different in G12B & SM1
Neil

> 
> 
> Best regards,
> Martin