linux-kernel - [PATCH 3/3] spi: dw: Write chip configuration before cs is set

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Date:   Fri,  2 Dec 2022 10:49:34 +0100
From:   Edmund Berenson <edmund.berenson@...ix.com>
To:     unlisted-recipients:; (no To-header on input)
Cc:     Edmund Berenson <edmund.berenson@...ix.com>,
        Lukasz Zemla <Lukasz.Zemla@...dward.com>,
        Serge Semin <fancer.lancer@...il.com>,
        Mark Brown <broonie@...nel.org>, linux-spi@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: [PATCH 3/3] spi: dw: Write chip configuration before cs is set

Using chips with different cpol, causes first communication
to fail on cpol change.
To avoid this issue write cr0 register before cs is set.

Suggested-by: Lukasz Zemla <Lukasz.Zemla@...dward.com>
Signed-off-by: Edmund Berenson <edmund.berenson@...ix.com>
---
 drivers/spi/spi-dw-core.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
index 57c9e384d6d4..c3da4fe3e510 100644
--- a/drivers/spi/spi-dw-core.c
+++ b/drivers/spi/spi-dw-core.c
@@ -93,6 +93,7 @@ static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
 void dw_spi_set_cs(struct spi_device *spi, bool enable)
 {
 	struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
+	struct dw_spi_chip_data *chip = spi_get_ctldata(spi);
 	bool cs_high = !!(spi->mode & SPI_CS_HIGH);
 	u8 enable_cs = 0;
 
@@ -106,8 +107,13 @@ void dw_spi_set_cs(struct spi_device *spi, bool enable)
 	 * Enable register no matter whether the SPI core is configured to
 	 * support active-high or active-low CS level.
 	 */
-	if (cs_high == enable)
+	if (cs_high == enable) {
+		dw_spi_enable_chip(dws, 0);
+		dw_writel(dws, DW_SPI_CTRLR0, chip->cr0);
+		dw_spi_enable_chip(dws, 1);
+
 		dw_writel(dws, DW_SPI_SER, BIT(enable_cs));
+	}
 	else
 		dw_writel(dws, DW_SPI_SER, 0);
 }
-- 
2.37.4