linux-kernel - Re: [PATCH v8 06/11] clk: meson: introduce a1-clkc common driver for all A1 clock controllers

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Message-ID: <20221202115841.xg3e56st7mk6lmbz@CAB-WSD-L081021>
Date:   Fri, 2 Dec 2022 14:58:41 +0300
From:   Dmitry Rokosov <ddrokosov@...rdevices.ru>
To:     Jerome Brunet <jbrunet@...libre.com>
CC:     <neil.armstrong@...aro.org>, <mturquette@...libre.com>,
        <sboyd@...nel.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <khilman@...libre.com>,
        <martin.blumenstingl@...glemail.com>, <jian.hu@...ogic.com>,
        <kernel@...rdevices.ru>, <rockosov@...il.com>,
        <linux-amlogic@...ts.infradead.org>, <linux-clk@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v8 06/11] clk: meson: introduce a1-clkc common driver for
 all A1 clock controllers

On Fri, Dec 02, 2022 at 12:36:50PM +0100, Jerome Brunet wrote:
> 
> On Fri 02 Dec 2022 at 01:56, Dmitry Rokosov <ddrokosov@...rdevices.ru> wrote:
> 
> > Generally, A1 SoC has four clock controllers on the board: PLL,
> > Peripherals, CPU, and Audio. The audio clock controller is different
> > from others, but the rest are very similar from a functional and regmap
> > point of view. So a it's good idea to generalize some routines for all
> > of them. Exactly, meson-a1-clkc driver contains the common probe() flow.
> >
> > Signed-off-by: Dmitry Rokosov <ddrokosov@...rdevices.ru>
> 
> I think you should leave this out for the initial submission. It makes
> harder to review.
> 
> In some case, these factorizations actually the maitenance harder.
> 
> There is also the s4 that is coming up. It looks similar to the A1 as
> well.
> 
> Let's wait for both them to land, see how it goes and then we'll decide
> if a factorization is appropriate.
> 

Jerome,

Sorry, let me double check a little bit that I get your point correctly.

Do you mean due to s4 development in parallel it's easier to have own
probe sequence for each driver in the first stage (until A1 and S4 clock
controllers not merged to upstream) and after think about some
"generalization", right?

...

-- 
Thank you,
Dmitry