linux-kernel - Re: [RFT PATCH v2 2/2] arm64: dts: qcom: sdm845: align TLMM pin configuration with DT schema

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Date:   Fri, 2 Dec 2022 06:36:54 -0800
From:   Doug Anderson <dianders@...omium.org>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc:     Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, Rob Clark <robdclark@...omium.org>,
        Fritz Koenig <frkoenig@...gle.com>
Subject: Re: [RFT PATCH v2 2/2] arm64: dts: qcom: sdm845: align TLMM pin
 configuration with DT schema

Hi,

On Fri, Dec 2, 2022 at 12:15 AM Krzysztof Kozlowski
<krzysztof.kozlowski@...aro.org> wrote:
>
> >>                         qup_uart6_4pin: qup-uart6-4pin-state {
> >> -
> >> -                               cts-pins {
> >> +                               qup_uart6_4pin_cts: cts-pins {
> >>                                         pins = "gpio45";
> >>                                         function = "qup6";
> >> -                                       bias-pull-down;
> >
> > After your patch, where is the above bias set for cheza, db845c,
> > oneplus, shift-axolotl, ...?
> >
> >
> >>                                 };
> >>
> >> -                               rts-tx-pins {
> >> +                               qup_uart6_4pin_rts_tx: rts-tx-pins {
> >>                                         pins = "gpio46", "gpio47";
> >>                                         function = "qup6";
> >> -                                       drive-strength = <2>;
> >> -                                       bias-disable;
> >
> > After your patch, where is the above bias / drive-strength set?
>
> They don't use 4-pin setup. If they use, I would assume they will
> override the entries just like sdm850 boards (where I override it to set
> these).
>
> Alternatively I can keep it in DTSI, but it is not really property of
> the SoC.

I see things like:

.../sdm845-cheza.dtsi:     pinctrl-0 = <&qup_uart6_4pin>;

...before your patch that would get the bias/drive strength from the
SoC dtsi, right? After your patch, you've removed it from the dtsi but
not added it to the board. ...so I think it's a net change. Did I mess
up / miss something?