linux-kernel - Re: [RFT PATCH v2 2/2] arm64: dts: qcom: sdm845: align TLMM pin configuration with DT schema

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <7ef76a8b-c45b-2a94-d0ad-9136757af684@linaro.org>
Date:   Fri, 2 Dec 2022 16:32:12 +0100
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Doug Anderson <dianders@...omium.org>
Cc:     Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, Rob Clark <robdclark@...omium.org>,
        Fritz Koenig <frkoenig@...gle.com>
Subject: Re: [RFT PATCH v2 2/2] arm64: dts: qcom: sdm845: align TLMM pin
 configuration with DT schema

On 02/12/2022 15:36, Doug Anderson wrote:
> Hi,
> 
> On Fri, Dec 2, 2022 at 12:15 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@...aro.org> wrote:
>>
>>>>                         qup_uart6_4pin: qup-uart6-4pin-state {
>>>> -
>>>> -                               cts-pins {
>>>> +                               qup_uart6_4pin_cts: cts-pins {
>>>>                                         pins = "gpio45";
>>>>                                         function = "qup6";
>>>> -                                       bias-pull-down;
>>>
>>> After your patch, where is the above bias set for cheza, db845c,
>>> oneplus, shift-axolotl, ...?
>>>
>>>
>>>>                                 };
>>>>
>>>> -                               rts-tx-pins {
>>>> +                               qup_uart6_4pin_rts_tx: rts-tx-pins {
>>>>                                         pins = "gpio46", "gpio47";
>>>>                                         function = "qup6";
>>>> -                                       drive-strength = <2>;
>>>> -                                       bias-disable;
>>>
>>> After your patch, where is the above bias / drive-strength set?
>>
>> They don't use 4-pin setup. If they use, I would assume they will
>> override the entries just like sdm850 boards (where I override it to set
>> these).
>>
>> Alternatively I can keep it in DTSI, but it is not really property of
>> the SoC.
> 
> I see things like:
> 
> .../sdm845-cheza.dtsi:     pinctrl-0 = <&qup_uart6_4pin>;
> 
> ...before your patch that would get the bias/drive strength from the
> SoC dtsi, right? After your patch, you've removed it from the dtsi but
> not added it to the board. ...so I think it's a net change. Did I mess
> up / miss something?

I missed something or rather my git grep failed. I'll bring them back to
DTSI.

Best regards,
Krzysztof