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Message-ID: <CAD=FV=U_kFLh1me+KGcg_hjC8_OhJtZ8ddsQyH2jNkw88ZG_aQ@mail.gmail.com>
Date: Fri, 2 Dec 2022 08:54:14 -0800
From: Doug Anderson <dianders@...omium.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 3/3] arm64: dts: qcom: sdm845: do not customize SPI0
pin drive/bias
Hi,
On Fri, Dec 2, 2022 at 7:57 AM Krzysztof Kozlowski
<krzysztof.kozlowski@...aro.org> wrote:
>
> Each board should define pin drive/bias for used busses. All boards
> using SPI0 (db845c and cheza) already do it, so drop the bias/drive
> strength from SoC DTSI.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
>
> ---
>
> Cc: Doug Anderson <dianders@...omium.org>
>
> Changes since v2:
> 1. New patch.
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 --
> 1 file changed, 2 deletions(-)
Reviewed-by: Douglas Anderson <dianders@...omium.org>
It's hard to review device trees without noticing things that are
inefficient / wrong. In case you want any others for your list:
a) As written today, `sdm845-db845c.dts` doesn't actually need to
override the `pinctrl` of `spi0` since it's the default. So you could
remove two extra lines of device tree.
b) Officially, db845c actually _should_ be overriding the pinctrl and
we should be doing something like what we did for sc7180 where we have
different definitions for "cs" and "cs_gpio" for the SPI lines. That's
because db845c is actually using "cs-gpio" mode for this SPI part and
thus GPIO3 should be marked as being "gpio", not "qup0". It doesn't
really matter functionality-wise on Linux because the Qualcomm pinctrl
driver will automatically re-mux the pin as a GPIO the moment the SPI
core tries to use it as such, but it's a little ugly.
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