linux-kernel - Re: [RESEND PATCH] soc: fsl: qe: request pins non-exclusively

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Sun, 4 Dec 2022 15:55:19 -0800
From:   Dmitry Torokhov <dmitry.torokhov@...il.com>
To:     Arnd Bergmann <arnd@...db.de>
Cc:     soc@...nel.org, Li Yang <leoyang.li@....com>,
        Qiang Zhao <qiang.zhao@....com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Linus Walleij <linus.walleij@...aro.org>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        linuxppc-dev@...ts.ozlabs.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-usb@...r.kernel.org
Subject: Re: [RESEND PATCH] soc: fsl: qe: request pins non-exclusively

On Sun, Dec 04, 2022 at 01:10:19PM +0100, Arnd Bergmann wrote:
> On Sun, Dec 4, 2022, at 05:50, Dmitry Torokhov wrote:
> >
> > SoC team, the problematic patch has been in next for a while and it
> > would be great to get the fix in to make sure the driver is not broken
> > in 6.2. Thanks!
> 
> I have no problem taking thsi patch, but I get a merge conflict that
> I'm not sure how to resolve:
> 
> 
> @@@ -186,23 -182,27 +180,43 @@@ struct qe_pin *qe_pin_request(struct de
>         if (WARN_ON(!gc)) {
>                 err = -ENODEV;
>                 goto err0;
> ++<<<<<<< HEAD
>  +      }
>  +      qe_pin->gpiod = gpiod;
>  +      qe_pin->controller = gpiochip_get_data(gc);
>  +      /*
>  +       * FIXME: this gets the local offset on the gpio_chip so that the driver
>  +       * can manipulate pin control settings through its custom API. The real
>  +       * solution is to create a real pin control driver for this.
>  +       */
>  +      qe_pin->num = gpio_chip_hwgpio(gpiod);
>  +
>  +      if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) {
>  +              pr_debug("%s: tried to get a non-qe pin\n", __func__);
>  +              gpiod_put(gpiod);
> ++=======
> +       } else if (!fwnode_device_is_compatible(gc->fwnode,
> +                                               "fsl,mpc8323-qe-pario-bank")) {
> +               dev_dbg(dev, "%s: tried to get a non-qe pin\n", __func__);
> ++>>>>>>> soc: fsl: qe: request pins non-exclusively
>                 err = -EINVAL;
> -               goto err0;
> +       } else {
> +               qe_pin->controller = gpiochip_get_data(gc);
> +               /*
> +                * FIXME: this gets the local offset on the gpio_chip so that
> +                * the driver can manipulate pin control settings through its
> +                * custom API. The real solution is to create a real pin control
> +                * driver for this.
> +                */
> +               qe_pin->num = desc_to_gpio(gpiod) - gc->base;
>         }
> 
> Could you rebase the patch on top of the soc/driver branch in the
> soc tree and send the updated version?

I see, it conflicts with:

	c9eb6e546a23 soc: fsl: qe: Switch to use fwnode instead of of_node

that is in next but not in soc/driver tree/branch. OK, I'll rebase and I
just noticed that I was leaking gpiod in case we could not locate gc
(unlikely but still...).

Thanks.

-- 
Dmitry