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Message-ID: <977DEE2E-FCD8-44AD-BB52-49EDF586B796@linaro.org>
Date: Tue, 06 Dec 2022 00:55:48 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
martin.petersen@...cle.com, jejb@...ux.ibm.com,
andersson@...nel.org, vkoul@...nel.org
CC: quic_cang@...cinc.com, quic_asutoshd@...cinc.com,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-phy@...ts.infradead.org, linux-scsi@...r.kernel.org,
ahalaney@...hat.com, abel.vesa@...aro.org, alim.akhtar@...sung.com,
avri.altman@....com, bvanassche@....org
Subject: Re: [PATCH v4 11/23] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8450 SoC
On 1 December 2022 20:43:16 GMT+03:00, Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org> wrote:
>UFS PHY in SM8450 SoC is capable of operating at HS G4 mode and the init
>sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance
>reusing the G4 init sequence of SM8350.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
>
>Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
>---
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
>diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>index 75e55c4181c9..96e03d4249da 100644
>--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>@@ -935,6 +935,14 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
> .serdes = sm8350_ufsphy_hs_b_serdes,
> .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
> },
>+ .tbls_hs_g4 = {
>+ .tx = sm8350_ufsphy_g4_tx,
>+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
>+ .rx = sm8350_ufsphy_g4_rx,
>+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
>+ .pcs = sm8350_ufsphy_g4_pcs,
>+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
>+ },
> .clk_list = sm8450_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
> .vreg_list = qmp_phy_vreg_l,
--
With best wishes
Dmitry
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