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Message-ID: <86359um7qy.wl-maz@kernel.org>
Date: Mon, 05 Dec 2022 11:04:37 +0000
From: Marc Zyngier <maz@...nel.org>
To: Thomas Gleixner <tglx@...utronix.de>
Cc: LKML <linux-kernel@...r.kernel.org>, x86@...nel.org,
Joerg Roedel <joro@...tes.org>, Will Deacon <will@...nel.org>,
linux-pci@...r.kernel.org, Bjorn Helgaas <bhelgaas@...gle.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jason Gunthorpe <jgg@...lanox.com>,
Dave Jiang <dave.jiang@...el.com>,
Alex Williamson <alex.williamson@...hat.com>,
Kevin Tian <kevin.tian@...el.com>,
Dan Williams <dan.j.williams@...el.com>,
Logan Gunthorpe <logang@...tatee.com>,
Ashok Raj <ashok.raj@...el.com>, Jon Mason <jdmason@...zu.us>,
Allen Hubbe <allenbh@...il.com>
Subject: Re: [patch V3 00/22] genirq, PCI/MSI: Support for per device MSI and PCI/IMS - Part 2 API rework
On Thu, 24 Nov 2022 23:24:07 +0000,
Thomas Gleixner <tglx@...utronix.de> wrote:
>
> This is V3 of the second part of the effort to provide support for per
> device MSI interrupt domains.
>
> Version 2 of this second part can be found here:
>
> https://lore.kernel.org/all/20221121083210.309161925@linutronix.de
Bandwidth is lacking to review such a series (let alone 3) in details,
but the direction of travel is the right one (per-device, per-bus MSI
domains are the natural way to deal with resources managed at the
device level).
I'm sure we'll find issues along the way, but this code is better in
the kernel than outside, so:
Acked-by: Marc Zyngier <maz@...nel.org>
M.
--
Without deviation from the norm, progress is not possible.
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