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Message-ID: <167025701595.1979605.16523500992587130634.robh@kernel.org>
Date: Mon, 5 Dec 2022 10:16:56 -0600
From: Rob Herring <robh@...nel.org>
To: Anup Patel <apatel@...tanamicro.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Andrew Jones <ajones@...tanamicro.com>,
Samuel Holland <samuel@...lland.org>,
linux-riscv@...ts.infradead.org,
Conor Dooley <conor.dooley@...rochip.com>,
Anup Patel <anup@...infault.org>,
Rob Herring <robh+dt@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>,
devicetree@...r.kernel.org, Palmer Dabbelt <palmer@...belt.com>,
linux-kernel@...r.kernel.org,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Palmer Dabbelt <palmer@...osinc.com>,
Atish Patra <atishp@...shpatra.org>,
Paul Walmsley <paul.walmsley@...ive.com>
Subject: Re: [PATCH v5 2/3] dt-bindings: timer: Add bindings for the RISC-V
timer device
On Thu, 01 Dec 2022 18:09:53 +0530, Anup Patel wrote:
> We add DT bindings for a separate RISC-V timer DT node which can
> be used to describe implementation specific behaviour (such as
> timer interrupt not triggered during non-retentive suspend).
>
> Signed-off-by: Anup Patel <apatel@...tanamicro.com>
> Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
> Acked-by: Palmer Dabbelt <palmer@...osinc.com>
> ---
> .../bindings/timer/riscv,timer.yaml | 52 +++++++++++++++++++
> 1 file changed, 52 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/riscv,timer.yaml
>
Reviewed-by: Rob Herring <robh@...nel.org>
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