linux-kernel - Re: [PATCH bpf v2] riscv, bpf: Emit fixed-length instructions for BPF_PSEUDO

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Message-ID: <0ade59ea-6863-4d68-607c-22e4b9405a0d@huaweicloud.com>
Date:   Tue, 6 Dec 2022 11:37:49 +0800
From:   Pu Lehui <pulehui@...weicloud.com>
To:     Björn Töpel <bjorn@...nel.org>,
        bpf@...r.kernel.org, linux-riscv@...ts.infradead.org,
        linux-kernel@...r.kernel.org
Cc:     Alexei Starovoitov <ast@...nel.org>,
        Daniel Borkmann <daniel@...earbox.net>,
        Andrii Nakryiko <andrii@...nel.org>,
        Martin KaFai Lau <martin.lau@...ux.dev>,
        Song Liu <song@...nel.org>, Yonghong Song <yhs@...com>,
        John Fastabend <john.fastabend@...il.com>,
        KP Singh <kpsingh@...nel.org>,
        Stanislav Fomichev <sdf@...gle.com>,
        Hao Luo <haoluo@...gle.com>, Jiri Olsa <jolsa@...nel.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Pu Lehui <pulehui@...wei.com>
Subject: Re: [PATCH bpf v2] riscv, bpf: Emit fixed-length instructions for
 BPF_PSEUDO_FUNC



On 2022/12/2 18:54, Björn Töpel wrote:
> Pu Lehui <pulehui@...weicloud.com> writes:
> 
>> From: Pu Lehui <pulehui@...wei.com>
>>
>> For BPF_PSEUDO_FUNC instruction, verifier will refill imm with
>> correct addresses of bpf_calls and then run last pass of JIT.
>> Since the emit_imm of RV64 is variable-length, which will emit
>> appropriate length instructions accorroding to the imm, it may
>> broke ctx->offset, and lead to unpredictable problem, such as
>> inaccurate jump. So let's fix it with fixed-length instructions.
>>
>> Fixes: 69c087ba6225 ("bpf: Add bpf_for_each_map_elem() helper")
>> Signed-off-by: Pu Lehui <pulehui@...wei.com>
>> Suggested-by: Björn Töpel <bjorn@...osinc.com>
>> ---
>>   arch/riscv/net/bpf_jit_comp64.c | 20 +++++++++++++++++++-
>>   1 file changed, 19 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
>> index eb99df41fa33..9723f34f7a06 100644
>> --- a/arch/riscv/net/bpf_jit_comp64.c
>> +++ b/arch/riscv/net/bpf_jit_comp64.c
>> @@ -139,6 +139,19 @@ static bool in_auipc_jalr_range(s64 val)
>>   		val < ((1L << 31) - (1L << 11));
>>   }
>>   
>> +/* Emit fixed-length instructions for address */
>> +static void emit_addr(u8 rd, u64 addr, struct rv_jit_context *ctx)
>> +{
>> +	u64 ip = (u64)(ctx->insns + ctx->ninsns);
>> +	s64 off = addr - ip;
>> +	s64 upper = (off + (1 << 11)) >> 12;
>> +	s64 lower = ((off & 0xfff) << 52) >> 52;
>> +
>> +	emit(rv_auipc(rd, upper), ctx);
>> +	emit(rv_addi(rd, rd, lower), ctx);
>> +}
> 
> Nice! Two instructions are better than 6! :-)
> 
> One final thing. Please add a sanity check, that the range is correct,
> e.g.:
> 
>    if (!(addr && in_auipc_addi_range(off)))
>       return -1;
> 

Hi Björn,

Sorry for replying so late. For BPF_PSEUDO_FUNC instruction, verifier 
will set insn[0].imm and insn[1].imm to 1 that make addr to 0x100000001 
before extra pass, and also ctx->insns is NULL in iteration stage, all 
of these make off out of range of AUIPC-ADDI range, and return failed. 
We could add some special handling at different stages, but that seems a 
little weird. By the way, I do not really like emit_addr function with 
return value.

While a proper address is at least 2B alignment, and the valid address 
is from 0xffffffff00000000 to 0xffffffffffffffff, we can make address 
shifed 1 place to right, and addr >> 1 will always in the range of 
AUIPC-ADDI range. We can get rid of the range detection. The 
implementation is as follows:

static void emit_addr(u8 rd, u64 addr, struct rv_jit_context *ctx)
{
          s64 imm = addr >> 1;
          s64 upper = (imm + (1 << 11)) >> 12;
          s64 lower = imm & 0xfff;

          emit(rv_lui(rd, upper), ctx);
          emit(rv_addi(rd, rd, lower), ctx);
          emit(rv_slli(rd, rd, 1), ctx);
}

What do you think?

Regards,
Lehui

> Have a look at emit_jump_and_link().
> 
> 
> Thanks!
> Björn