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Message-Id: <20221206112330.78431-1-angelogioacchino.delregno@collabora.com>
Date:   Tue,  6 Dec 2022 12:23:25 +0100
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
To:     matthias.bgg@...il.com
Cc:     robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        nfraprado@...labora.com, kernel@...labora.com,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
Subject: [PATCH 0/5] Add CPU caches information for some MediaTek SoCs

In devicetrees for MediaTek SoCs the CPU caches information, if
present, is incomplete as it misses cache size, cache line size
and number of cache sets which, in turn, will also prevent any
cache associativity calculation.

For all of the SoCs that I know and/or I have information for,
I've added the right information for I/D, L2 and L3 where present.
This will also make the cacheinfo driver to correctly export the
CPU cache information to sysfs.

AngeloGioacchino Del Regno (5):
  arm64: dts: mt8195: Add complete CPU caches information
  arm64: dts: mt8192: Add complete CPU caches information
  arm64: dts: mt8186: Add complete CPU caches information
  arm64: dts: mt8183: Add complete CPU caches information
  arm64: dts: mt6795: Add complete CPU caches information

 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 50 ++++++++++++++++
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 74 ++++++++++++++++++++++++
 arch/arm64/boot/dts/mediatek/mt8186.dtsi | 58 +++++++++++++++++++
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 +++++++++++++++++++
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 58 +++++++++++++++++++
 5 files changed, 298 insertions(+)

-- 
2.38.1

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