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Message-ID: <Y49k1k8ayI9/rK+R@hovoldconsulting.com>
Date: Tue, 6 Dec 2022 16:50:46 +0100
From: Johan Hovold <johan@...nel.org>
To: Brian Masney <bmasney@...hat.com>
Cc: andersson@...nel.org, krzysztof.kozlowski+dt@...aro.org,
agross@...nel.org, konrad.dybcio@...aro.org, robh+dt@...nel.org,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, quic_shazhuss@...cinc.com,
psodagud@...cinc.com, ahalaney@...hat.com, echanude@...hat.com
Subject: Re: [PATCH v3] arm64: dts: qcom: sa8540p-ride: enable PCIe support
On Fri, Dec 02, 2022 at 07:09:18AM -0500, Brian Masney wrote:
> Add the vreg_l11a, pcie3a, pcie3a_phy, and tlmm nodes that are necessary
> in order to get PCIe working on the QDrive3.
> @@ -158,6 +186,31 @@ &remoteproc_nsp1 {
> status = "okay";
> };
>
> +&tlmm {
> + pcie3a_default: pcie3a-default-state {
> + perst-pins {
> + pins = "gpio151";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + clkreq-pins {
> + pins = "gpio150";
> + function = "pcie3a_clkreq";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + wake-pins {
> + pins = "gpio56";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +};
> +
The pin configuration nodes typically go last after a
/* PINCTRL */
delimiter as this section tends to become rather long.
> &ufs_mem_hc {
> reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
Johan
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